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6.5 TLSB Interface
All TLSB bus transactions consist of one command/address cycle on the ad-
dress bus and two data cycles on the data bus. The TLSB bus implements
separate address and data buses to reduce memory latency, to allow the
TLSB to adapt to different speed memories, and a range of bus cycle times
(10 to 30 ns).
To create a low latency system, memory is addressed by a unique 4-bit
bank number transmitted on the TLSB address bus. The I/O port per-
forms a bank decode to decide if it can issue the request. Therefore, the
I/O port transmits the bank number along with the address and command
field on the address bus. This simplifies the memory address decoding and
permits fast memory addressing.
The address bus allows flow control by the use of the TLSB_ARB_SUP sig-
nal. This tells the commander nodes to stop arbitrating for the bus and
prevents further addresses from going out on the address bus.
Data bus sequencing is controlled by the slave node, which waits until the
sequence count reaches the correct count for that transaction, then takes
control of the data bus and asserts TLSB_SEND_DATA and
TLSB_SEQ<3:0> five cycles (assuming TLSB_HOLD is not asserted) be-
fore transferring data through the data bus. The sequence count guaran-
tees that data is driven onto the data bus in the same order as com-
mand/addresses are driven onto the address bus. For CSR broadcast
writes it is the commander's responsibility to sequence the data bus.
In an I/O port transaction, the request is asserted (for at least one cycle)
followed by the command/address/bank number. Two cycles after the C/A
cycle, the TLSB_CMD_ACK is given. When the slave node is ready to
transfer on the data bus, it asserts TLSB_SEND_DATA and TLSB_SEQ-
<3:0>. Five cycles later (assuming TLSB_HOLD is not asserted), the data
bus transfer takes place.
TLSB_SEND_DATA must be handled in a special way if two memory read
transactions are retired back-to-back and TLSB_HOLD is asserted in re-
sponse to the first TLSB_SEND_DATA. The timing of TLSB_HOLD is
such that there is no time to prevent the second TLSB_SEND_DATA being
sent. The second TLSB_SEND_DATA must be held asserted until
TLSB_HOLD is released. TLSB_SEND_DATA is ignored in any cycle in
which TLSB_HOLD is asserted and for the first cycle after TLSB_HOLD
deassertion.
6.5.1 Transactions
Table 6-7 summarizes the TLSB transaction types that the I/O port initi-
ates and responds to.
I/O Port 6-23
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