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The memory interface to the TLSB consists of three parts:
5.1 Control Address Interface
The control address interface (CTL) is the primary controller chip for the
TLSB memory. It receives the address and control signals from the TLSB
and generates the DRAM address and control signals in response to them.
The CTL contains the major functions of:
This chapter discusses the first three items. The self-test address and con-
trol logic is described in Chapter 4.
5.1.1 TLSB Control
The TLSB memory control structure consists of the following functional
blocks:
• Control address interface
• Memory data interface
• CSR interface
• TLSB control (through the TLSB state machines)
• DRAM control (through the DRAM state machines)
• Command/address/RAS decode logic
• Self-test address and control logic
• Bank 0 state machine (TLSM)
• Bank 1 state machine (TLSM)
• CSR state machine (TLSM)
• TLSB input latches
• TLSB bus monitor
• TLSB command decode
• TLSB bank match logic
• TLSB address, command, and bank number parity checkers
• TLSB sequence control
• TLSB bank available flags
Chapter 5
Memory Interface
Memory Interface 5-1
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