Cpu Module Registers - DEC AlphaServer 8200 Technical Manual

Table 7-20 CPU Module Registers
Mnemonic Name
Module Registers
Diagnostic Setup Register
TLDIAG
DTag Data Register
TLDTAGDATA
DTag Status Register
TLDTAGSTAT
TLMODCONFIG CPU Module Configuration Register
Console Communications Register 0 for CPU0
TLCON00
DIGA Communications Test Register 0 for DIGA1
TLCON0A
DIGA Communications Test Register 0 for DIGA2
TLCON0B
DIGA Communications Test Register 0 for DIGA3
TLCON0C
Console Communications Register 0 for CPU1
TLCON10
TLCON1A DIGA Communications Test Register 1 for DIGA1
DIGA Communications Test Register 1 for DIGA2
TLCON1B
DIGA Communications Test Register 1 for DIGA3
TLCON1C
Console Communications Register 1 for CPU0
TLCON01
Console Communications Register 1 for CPU1
TLCON11
TLEPAERR ADG Error Register
DIGA Error Register
TLEPDERR
MMG Error Register
TLEPMERR
Voltage Margining Register
TLEP_VMG
Data Mover Command Register
TLDMCMD
Data Mover Source Address Register
TLDMADRA
TLDMADRB Data Mover Destination Address Register
Performance Monitor Command Register
TLPM_CMD
Total number of cycles since start bit was set
TLPM_TOT_CYC
Total average read latency seen by EV5 (DECchip 21164)
TLPM_EV5_LAT
Average latency for individual reads
TLPM_RD_LAT
TLPM_SYS_OWN Number of cycles for which system owned the add/cmd bus
Command Silo Register
TLPM_CMD_SILO
Number of lock commands acknowledged
TLPM_LOCK
Number of memory barriers acknowledged
TLPM_MB
Number of set Dirtys issued by DECchip 21164
TLPM_SD_TOTAL
TLPM_SD_ACKED Number of those set Dirtys that were acknowledged
Number of CSR read commands
TLPM_RD_CSR
Number of memory space read miss commands
TLPM_RD
Number of read miss mod commands
TLPM_RD_MOD
Number of read miss STxC commands
TLPM_RD_STC
Number of B-cache victims
TLPM_VICTIM
TLPM_WR_CSR Number of CSR write commands
Number of write block commands acknowledged
TLPM_WR
Number of write block lock commands acknowledged
TLPM_WR_LOCK
Number of invalidates from system
TLPM_INVAL
Number of set Shared bits from system
TLPM_SET_SHRD
TLPM_RD_DIRTY Number of read Dirty bits from system
Address Silo Register
TLPM_ADR_SILO
1 This register is used by performance analysts to monitor the overall performance of the CPU module.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address
BB+1000
BB+1040
BB+1080
BB+10C0
BB+1200
BB+1240
BB+1280
BB+12C0
BB+1300
BB+1340
BB+1380
BB+13C0
BB+1400
BB+1440
BB+1500
BB+1540
BB+1580
BB+15C0
BB+1600
BB+1680
BB+16C0
BB+1800
BB+1840
BB+1880
BB+18C0
1
BB+1900
BB+1940
BB+1980
BB+19C0
1
BB+1A00
1
BB+1A40
BB+1A80
1
BB+1AC0
BB+1B00
BB+1B40
BB+1B80
BB+1BC0
1
BB+1C00
1
BB+1C40
BB+1C80
BB+1CC0
BB+1D00
BB+1D40
System Registers 7-45