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Table 5-4
Eight Strings—512MB/2048MB Row/Column Address Bit Swapping
DRAM Type
No. of Banks
Interleaved
DRAM Address
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
10
Row_Adr<0>
11
Row_Adr<0>
Row_Adr<0>
12
13
Row_Adr<0>
14
Row_Adr<0>
15
Row_Adr<0>
16
Row_Adr<0>
x(21)
Row_Adr<0>
Row_Adr<0>
x(22)
21
Col_Adr<0>
22
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
17
Col_Adr<0>
18
Col_Adr<0>
19
Col_Adr<0>
Col_Adr<0>
20
Mod_Sel<0>
Mod_Sel<0>
Mod_Sel<0>
Bank_Sel<0>
Ras_Sel<0>
Ras_Sel<1>
Key to 4M DRAM Unused Row Addresses/Ras_Sel and Mod_Sel:
x(n) : Don't Care. (n) is the address bit driven even though it is not used by the DRAMs.
x : Don't Care. No address bits are involved in this decision.
5-8 Memory Interface
4 Mbit
1
2
4
7
7
7
8
8
8
9
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
x(21)
x(21)
x(22)
x(22)
21
21
22
22
3
23
23
4
24
24
5
5
25
6
6
6
17
17
18
18
19
19
20
20
x
1
1
x
x
2
x
x
x
1
2
3
2
3
4
3
4
5
16 Mbit
8
1
2
7
7
7
8
8
8
9
9
9
10
10
10
11
11
11
12
12
12
13
13
13
14
14
14
15
15
15
16
16
16
x(21)
21
21
x(22)
22
22
21
23
23
22
24
24
23
25
25
24
4
26
25
5
5
26
6
6
17
17
17
18
18
18
19
19
19
20
20
20
1
x
1
2
x
x
3
x
x
4
1
2
5
2
3
6
3
4
4
8
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
21
21
22
22
23
23
24
24
25
25
26
26
27
27
6
28
17
17
18
18
19
19
20
20
1
1
2
2
x
3
3
4
4
5
5
6
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