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commands are necessary to ensure an atomic operation and maintain
cache coherency.
6.5.2.3
Bank Collision Effect on Priority
A bank collision occurs when two commanders request the same bank, the
first one wins, the second one gets the bus 2 cycles later and finds that it is
not allowed to access that bank. Since it is too late to withdraw the re-
quest, a no-op command must be placed on the address bus. Any time a
no-op is put on the bus the arbitration is considered false. Because relative
bus priorities are updated only when a real command is acknowledged on
the bus, the false arbitration does not cause that node to lose priority.
6.5.2.4
Look-Back-Two
The look-back-two mechanism is needed to prevent a low-priority device
from being held off by higher priority devices that are false (or early) arbi-
trating. This is done by assigning a higher priority to requests that have
been continuously asserted for more than two cycles (real requests).
6.5.2.5
Arbitration Suppress
To limit the number of outstanding transactions on the bus, a module can
assert ARB_SUP. This prevents devices from arbitrating for the address
bus until ARB_SUP is deasserted. If ARB_SUP is asserted during an arbi-
tration cycle, the arbitration is allowed to complete and any further arbi-
trations are suppressed. This has an adverse impact on the minimum la-
tency requirement for the node 8 I/O port.
The number of outstanding transactions is selected by setting the ICC-
MSR<SUP_CTL> bits. This causes the I/O port to assert TLSB_ARB_SUP
after 2, 4, 8, or 16 (default) outstanding transactions.
6.5.3 Error Detection Schemes
The TLSB uses ECC protection for all memory and CSR data cycles, odd
parity protection on all command/address cycles, and transmit check logic
by all nodes that are responsible for driving the bus.
All command/address cycles are protected by two odd parity bits.
TLSB_ADR<30:5> are protected by the first parity bit.
TLSB_ADR<39:31>, TLSB_ADR<4:3>, TLSB_CMD<2:0>, and
TLSB_BANK_NUM<3:0> are protected by the second parity bit.
6-34 I/O Port
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