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tected, the I/O port does not issue the transaction on the TLSB. It simply
aborts that transaction by transmitting a UTV_ERROR_A (or B) code
across its internal TL_CMD bus to each IDR. The I/O port then posts an
IPL 17 interrupt on the TLSB, if enabled by ICCNSE<INTR_NSES>.
6.7.8 Data Bus Errors
Data bus errors are either ECC-detected errors on data transfers or control
errors on the data bus. In addition, all I/O port transceivers on the TLSB
check the data received from the bus against the expected data driven on
the bus.
The I/O port slices the TLSB_D<255:0> and TLSB_ECC<31:0> signals into
four parts, each containing 64 bits of data and 8 bits of ECC as follows:
The I/O port handles error detection on these signals independently in
each slice, setting error bits in a corresponding TLESRn register. The con-
tents of the four TLESRn registers is summarized in the TLBER register.
Broadcasting of the error is determined by the error type and whether or
not broadcasting of the error type is enabled.
6.7.8.1
Single-Bit ECC Errors
A single bit error on a memory data transfer is detected by the I/O port's
ECC checking logic. The I/O port both checks and corrects the data. If the
I/O port detects a single-bit ECC error, it logs the error in its TLESRn reg-
ister by setting either <CRECC> or <CWECC>, depending on whether a
read or write command failed. If the error was detected on data that the
I/O port was writing to memory, then the TLESR<TDE> and TL-
BER<DTDE> bits are also set.
A CRECC error sets <CRDE> in the I/O port's TLBER register. A CWECC
error sets <CWDE> in the I/O port's TLBER register.
When the I/O port detects a single-bit data error, it asserts TLSB_DATA_
ERROR to signal the other nodes of the error. If correctable error inter-
rupts are not disabled by TLCNR<CWDD> and TLCNR<CRDD>, and ICC-
NSE<INTR_NSES> is set, an IPL 17 interrupt is posted to the proces-
sor(s).
The I/O port also latches the failing syndrome in the TLESRn registers, in-
dicating which cycle(s) failed during the transaction.
6.7.8.2
Double-Bit ECC Errors
A double-bit error on a data transfer is detected by the I/O port's ECC
checking logic. The I/O port logs the error in its TLESRn register by set-
6-72 I/O Port
• TLSB_D<63:0> and TLSB_ECC<7:0> are handled by the IDR_0 gate
array
• TLSB_D<127:64> and TLSB_ECC<15:8> are handled by the IDR_1
gate array
• TLSB_D<191:128> and TLSB_ECC<23:16> are handled by the IDR_2
gate array
• TSB_D<255:192> and TLSB_ECC<31:24> are handled by the IDR_3
gate array
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