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STAIR—Self-Test Address Isolation Register
Address
BB + 0000 18C0
Access
R/W
The STAIR register is used to isolate self-test failures to a given ad-
dress segment or segments in the case of multiple failures in a
module. This register breaks up a memory module into at most 32
distinct address segments, which would be the case of a 2-Gbyte
module. Each segment maps 64 Mbytes (1 meg 64-byte blocks) of
memory independent of the selected DRAM (4 Mbit, 16 Mbit).
When a bit is set following completion of self-test, the correspond-
ing address segment has failed. This information can be used by
the console to map out bad areas of memory. The contents of this
register will be cleared when bit <7> (POEMC) in the MDRA regis-
ter is asserted while self-test is executed in POEM mode.
31
Table 7-44 STAIR Register Bit Definitions
Name
Bit(s)
<31:0>
STAIR
Address segments are mapped according to total possible module capacity
(maximum of 8 strings 2-Gbyte capacity), not to the actual capacity imple-
mented, which may be less. In Table 7-45 all addresses are listed as physi-
cal byte addresses.
STAIR
Type
Function
W1C, 0
Self-Test Failing Address Range. A bit in
this register is set when self-test detects a data
mismatch error in the corresponding address
segment. The address range specified in Table
7-45 indicates the failing address segment.
0
BXB-0732-93
System Registers 7-93
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