Address Bus Commands; Tlsb Address Bus Commands - DEC AlphaServer 8200 Technical Manual

Two signals are used to provide parity protection on the address bus dur-
ing all command cycles. TLSB_CMD_PAR is asserted to generate odd par-
ity for the signals TLSB_CMD<2:0>, TLSB_BANK_NUM<3:0>,
TLSB_ADR<39:31>, and TLSB_ADR<4:3>. TLSB_ADR_PAR is asserted
to generate odd parity for the signals TLSB_ADR<30:5>.
When not in use, idle address bus cycles have a predictable value, called
the default bus value. The default value is given in Table 2-1.

2.2.6 Address Bus Commands

Table 2-4 lists the commands used by the TLSB.
Table 2-4

TLSB Address Bus Commands

No-op
The device that won arbitration has decided to null the command. No ac-
tion is taken. Priority is not updated. The command is not acknowledged,
and the bus sequence number is not incremented. TLSB_ADR<39:5> and
TLSB_BANK_NUM<3:0> are not used and their contents are Unpredict-
able.
Victim
Write the block specified by the address and bank number into memory
only. Nonmemory devices do not need to do coherency checks.
Read
Read the block specified by the address and bank number and return that
data over the bus.
Write
Write the block specified by the address and the bank number. Any CPU
containing that block can take an update or an invalidate based on that
CPU's update protocol.
Read Bank Lock
Used by an I/O port to do a Read-Modify-Write. Locks access to the bank
until followed by a Write Bank Unlock. This command reads the block
specified by the address and bank number, and locks the bank.
• No-op command cycles
TLSB_CMD
<2:0> Command
No-op
000
Victim
001
Read
010
Write
011
100 Read Bank Lock
Write Bank Unlock
101
CSR Read
110
CSR Write
111
Description
Nulled command
Victim eviction
Memory read
Memory write, or write update
Read memory bank, lock
Write memory bank, unlock
Read CSR data
Write CSR data
TLSB Bus 2-17