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This timeout can be disabled by software. The <DTOD> bit in the TLCNR
register prevents <DTO> from setting. It does not clear <DTO> if already
set.
2.4.4.5
Data Status Errors
The TLSB_STATCHK signal is used as a check on TLSB_SHARED and
TLSB_DIRTY. When TLSB_SHARED and TLSB_DIRTY are expected to
be valid on the bus, TLSB_STATCHK is read and compared with them. If
either TLSB_SHARED or TLSB_DIRTY are received asserted while
TLSB_STATCHK is deasserted or if TLSB_STATCHK is asserted while
TLSB_SHARED and TLSB_DIRTY are both deasserted, <DSE> is set in
the TLBER register and TLSB_FAULT is asserted four cycles after the in-
correct signals.
2.4.4.6
Transmit Check Errors
All drivers on the TLSB check the data received from the bus against the
expected data driven on the bus. If there is a discrepancy between the
driven and received data, a transmit check error is logged in the TLBER.
Two types of transmit checks are used. They are described in Section
2.4.3.1.
The TLSB_D<255:0> and TLSB_ECC<31:0> fields are level-checked when
a node is driving data on the bus. A mismatch results in setting <TCE> in
a TLESRn register. Since ECC is checked on the data received from the
bus, a TCE error may also result in one of <UECC>, <CWECC>, or
<CRECC> bits being set. If <TCE> should set without any other error bit
(a case where other nodes receive this data and assume it is good), <FD-
TCE> sets in the TLBER register and the node asserts TLSB_FAULT ten
cycles after the second of the two data cycles in error.
TLSB_DATA_VALID<3:0> are level-checked when a node is driving data
on the bus. A mismatch results in setting <DVTCE> in a TLESRn regis-
ter. The use of these signals is implementation specific and the error is
considered a soft error, allowing the implementation to provide data cor-
rection. Setting <DVTCE> in a TLESRn register results in either <CRDE>
or <CWDE> (depending on command code) being set in the TLBER regis-
ter.
TLSB_SEND_DATA, TLSB_SHARED, TLSB_DIRTY, TLSB_HOLD,
TLSB_STATCHK, and TLSB_DATA_ERROR are checked only when each
is being asserted by the node. A mismatch sets <DCTCE> in the TLBER
register and asserts TLSB_FAULT four cycles after the signal should have
asserted.
TLSB_SEQ<3:0> are level-checked whenever a node asserts
TLSB_SEND_DATA. A mismatch sets <DCTCE> and asserts
TLSB_FAULT four cycles after the incorrect assertion.
2.4.4.7
Multiple Data Bus Errors
Hard and soft data bus errors are cumulative. Should a second error oc-
cur, TLSB_DATA_ERROR is asserted a second time. If the error is of a
different type than the first, an additional error bit is set in the TLBER
register.
TLSB Bus 2-41
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