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BER<BAE> is set if the Write Bank Unlock command appears on the bus
before the second data cycle of the preceding Read Bank Lock command.
If any node receives a CSR access command (to any address) while a CSR
command is in progress, the node sets TLBER<BAE> and asserts
TLSB_FAULT six cycles after the command. A node sets TLBER<BAE> if
a new CSR command appears on the bus in or prior to the second data cy-
cle of the preceding CSR command. A node also sets TLBER<BAE> if a
new CSR command appears on the bus sooner than seven cycles after a
previous CSR command that was not acknowledged.
Nodes latch the address, command, and bank number in the TLFADRn
registers upon setting this error.
2.4.3.7
Memory Mapping Register Error
A commander node translates a memory address to a bank number before
issuing every command. This translation is performed by examining the
contents of the TLMMRn registers in the node. The <MMRE> error bit is
set if no bank number can be determined from the memory address.
This error is not broadcast. Handling of the error within the commander is
implementation specific. If the address is issued on the bus, the command
must be no-op.
2.4.3.8
Multiple Address Bus Errors
Address bus errors are cumulative. Should a second error condition occur,
TLSB_FAULT may be asserted a second time. If the error is of a different
type than the first, an additional error bit sets in the TLBER register.
Software must ensure that no error bits are set after the receipt of
TLSB_FAULT by resetting all logic immediately.
2.4.3.9
Summary of Address Bus Errors
Table 2-10 shows all the address bus errors, which nodes are responsible
for detecting the errors, and what error signals are asserted.
2-38 TLSB Bus
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