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2.2.3.4
Bank Available Status
TLSB_BANK_AVL indicates that a bank is available for use. When not
asserted, no requests except Write Bank Unlock can be issued to that
bank.
Each memory bank has one of the TLSB_BANK_AVL<15:0> signals as-
signed to it by the console. The number of the TLSB_BANK_AVL bit corre-
sponds to the bank number assigned to that bank. TLSB_BANK_AVL is
deasserted two cycles after the command is driven on the bus, and is as-
serted four cycles before the bank is available to accept new commands.
The earliest the TLSB_BANK_AVL bit can be asserted is two cycles follow-
ing the time when the shared and dirty status is available on the bus (that
is, TLSB_HOLD is deasserted). This is required so that CPUs have time
to update the tag status of the block before another command can be tar-
geted at that block.
I/O devices can use bus commands Read Bank Lock and Write Bank Un-
lock to guarantee atomic Read-Modify-Write access to a block. The
TLSB_BANK_AVL bit is deasserted in response to a Read Bank Lock and
remains deasserted until a Write Bank Unlock is issued. An I/O device can
arbitrate for a busy bank, but only when the bank is busy because of a
Read Bank Lock that it issued. The I/O device must control the sequence
as follows:
2.2.3.5
Address Bus Sequencing
For the data bus to return data in order, each valid bus command must be
tagged in the slave and commander TLSB interface with a sequence num-
ber. A maximum of 16 outstanding transactions are allowed on the bus at
any one time. This requires a wrapping 4-bit count. The first command fol-
lowing a reset sequence must be tagged with a sequence number of zero.
When a command is acknowledged, the sequence number is held by the
slave and commander. When the data bus sequence counter matches the
tagged sequence, the data transfer takes place.
All nodes increment their address bus sequence counters on the receipt of
a command acknowledge. When a command is nulled (for example, due to
false arbitration or bank conflict), the sequence number is not incre-
mented.
All nodes watch the data bus sequence. If a transaction is lost or incor-
rectly sequenced, the TLSB node interfaces will detect an illegal sequence.
Sequence errors are regarded as system fatal.
• Read Bank Lock must be followed by a Write Bank Unlock as the next
operation to that bank.
• The earliest the I/O device can request the bus for the Write Bank Un-
lock command is two cycles following the time when the shared and
dirty status for the Read Bank Lock command is available on the bus
(that is, TLSB_HOLD is deasserted).
• The Write Bank Unlock must be issued as soon as possible after the
data from the Read Bank Lock command is received.
• Intervening commands to other banks may be issued.
TLSB Bus 2-11
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