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Table 7-11 TLESRn Register Bit Definitions (Continued)
Name
Bit(s)
<23>
CPU1
RSVD
RSVD
<22>
CPU0
<21>
CRECC
<20>
CWECC
<19>
UECC
<18>
DVTCE
RSVD
<17>
TCE
Type
Function
RO, 0
CPU 1. When set together with <TDE>, indicates
that CPU1 was involved with sourcing the data er-
ror. This bit is Unpredictable when <TDE> is clear
and also when CRECC, CWECC, and UCE are zero.
R0
Memory: Reserved. Reads as zero.
R0
I/O: Reserved. Reads as zero.
RO, 0
CPU 0. When set together with <TDE>, indicates
that CPU0 was involved with sourcing the data er-
ror. This bit is Unpredictable when <TDE> is clear
and also when CRECC, CWECC, and UCE are zero.
Memory: Reserved. Reads as zero.
I/O: Reserved. Reads as zero.
W1C, 0
Correctable Read ECC Error. Set when an error
occurs during a read command. This is a soft error.
W1C, 0
Correctable Write ECC Error. Set when an error
occurs during a write command. This is a soft error.
W1C, 0
Uncorrectable ECC Error. Set when an uncor-
rectable syndrome is detected, or if a correctable syn-
drome is detected on receipt of CSR data which the
node is unable to correct. This is a hard error.
W1C, 0
I/O, CPU: Data Valid Transmit Check Error.
Set when a transmit check error is detected on the
TLSB_DATA_VALID signal covered by this register.
This is a soft error.
R0
Memory: Reserved. Reads as zero.
W1C, 0
Transmit Check Error. Set when a transmit
check error is detected on the TLSB_D or
TLSB_ECC signals covered by the TLESRn register.
This is a system fatal error if not accompanied by a
CRECC, CWECC, or UECC (I/O port only) error in
the same data cycle.
System Registers 7-27
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