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DEC AlphaServer 8200 Technical Manual

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AlphaServer 8200/8400
System Technical Manual
Order Number EK–T8030–TM. A01
The Digital AlphaServer 8200 and 8400 systems are designed around the
DECchip 21164 CPU. The TLSB is the system bus that supports nine nodes in
the 8400 system and five nodes in the 8200 system. The AlphaServer 8400 can
be configured with up to six single or dual processor CPU modules (KN7CC),
seven memory modules (MS7CC), and three I/O modules (KFTHA and
KFTIA). One slot is dedicated to I/O and is normally occupied by the inte-
grated I/O module (KFTIA) that supports PCI bus, XMI, and Futurebus+
adapters. All other nodes can be interchangeably configured for CPU or mem-
ory modules. The AlphaServer 8200 can be configured with up to three CPU
modules, three memory modules, and three I/O modules.
digital equipment corporation
maynard, massachusetts

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  • Page 1 I/O module (KFTIA) that supports PCI bus, XMI, and Futurebus+ adapters. All other nodes can be interchangeably configured for CPU or mem- ory modules. The AlphaServer 8200 can be configured with up to three CPU modules, three memory modules, and three I/O modules.
  • Page 2 The following are trademarks of Digital Equipment Corporation: AlphaGeneration, AlphaServer, DEC, DECchip, DEC LANcontroller, OpenVMS, StorageWorks, VAX, the AlphaGeneration logo, and the DIGITAL logo. OSF/1 is a registered trademark of the Open Software Foundation, Inc. Prestoserve is a trademark of Legato Systems, Inc.

  • Page 3: Table Of Contents

    Contents Preface ............................xv Chapter 1 Overview Configuration ........................ 1-1 Bus Architecture ......................1-2 CPU Module ........................1-3 1.3.1 DECchip 21164 ...................... 1-3 1.3.2 Backup Cache ......................1-4 1.3.3 TLSB Interface ....................... 1-4 1.3.4 Console Support Hardware ..................1-4 Memory Module ......................1-4 I/O Architecture ......................
  • Page 4 2.2.4.3 Address Bus Transactions ................2-12 2.2.4.4 Module Transactions ..................2-12 2.2.4.5 Address Bus Priority ..................2-12 2.2.4.6 Address Bus Request ..................2-13 2.2.4.7 Asserting Request ..................2-13 2.2.4.8 Early Arbitration ................... 2-13 2.2.4.9 False Arbitration Effect on Priority .............. 2-14 2.2.4.10 Look-Back-Two ....................
  • Page 5 2.4.3.8 Multiple Address Bus Errors ................. 2-38 2.4.3.9 Summary of Address Bus Errors ..............2-38 2.4.4 Data Bus Errors ....................2-39 2.4.4.1 Single-Bit ECC Errors ................... 2-40 2.4.4.2 Double-Bit ECC Errors .................. 2-40 2.4.4.3 Illegal Sequence Errors .................. 2-40 2.4.4.4 SEND_DATA Timeout Errors ...............
  • Page 6 Chapter 4 Memory Subsystem Internal Cache ....................... 4-1 4.1.1 Instruction Cache ....................4-1 4.1.2 Data Cache ......................4-1 4.1.3 Second-Level Cache ....................4-2 Backup Cache ........................ 4-2 4.2.1 Cache Coherency ....................4-2 4.2.2 B-Cache Tags ......................4-3 4.2.3 Updates and Invalidates ..................4-4 4.2.4 Duplicate Tags ......................
  • Page 7 5.2.2.3 CSR Write Data ECC Check ................. 5-10 5.2.2.4 Forcing Write Errors for Diagnostics ............2-15 5.2.2.5 Write Data Out Selection ................2-15 5.2.3 Read Data Output Logic ..................2-16 5.2.3.1 Read Data Buffers ..................2-16 5.2.3.2 Read Data Path ECC Algorithm ..............5-11 5.2.3.3 CSR Read Data ECC ..................
  • Page 8 6.5.3 Error Detection Schemes ..................6-34 Hose Interface ......................6-35 6.6.1 Hose Protocol ....................... 6-35 6.6.2 Window Space Mapping ..................6-36 6.6.2.1 Sparse Address Mapping ................6-37 6.6.2.2 Dense Address Mapping ................6-37 6.6.3 Hose Signals ......................6-37 6.6.4 Hose Packet Specifications ................... 6-39 6.6.4.1 Down Hose Packet Specifications ..............
  • Page 9 Chapter 7 System Registers Register Conventions ....................7-1 Register Address Mapping ................... 7-2 TLSB Registers ......................7-4 TLDEV—Device Register ..................7-5 TLBER—Bus Error Register ................. 7-7 TLCNR—Configuration Register ................ 7-14 TLVID—Virtual ID Register ................7-19 TLMMRn—Memory Mapping Registers ............7-21 TLFADRn—Failing Address Registers ..............
  • Page 10 DDR0:3—Data Diagnostic Registers ..............7-106 I/O Port-Specific Registers ..................7-109 RMRR0-1—Memory Channel Range Registers ..........7-110 ICCMSR—I/O Control Chip Mode Select Register ........... 7-112 ICCNSE—I/O Control Chip Node-Specific Error Reg ........7-117 ICCDR—I/O Control Chip Diagnostic Register ..........7-122 ICCMTR—I/O Control Chip Mailbox Transaction Reg ........7-125 ICCWTR—I/O Control Chip Window Transaction Reg ........
  • Page 11 6-35 Integrated I/O Section of the KFTIA ..............6-81 Mailbox Data Structure ..................7-33 Tables Digital AlphaServer 8200/8400 Documentation ............xvii Related Documents ....................... xix TLSB Bus Signals ......................2-3 TLSB Physical Node Identification ................2-5 Interleave Field Values for Two-Bank Memory Modules ........... 2-9 TLSB Address Bus Commands ..................
  • Page 12 TLSB Node Base Addresses ..................2-28 TLSB CSR Address Mapping ..................2-29 Mailbox Data Structure ....................2-31 2-10 Address Bus Error Summary ..................2-39 2-11 Signals Covered by TLESRn Registers ..............2-39 2-12 Data Bus Error Summary ..................2-42 Directly Addressable Console Hardware ..............3-6 TLSB Wrapping ......................
  • Page 13 6-30 DMA Masked Write Packet Sizes ................6-58 6-31 DMA Unmasked Write Packet Description ............... 6-60 6-32 INTR/IDENT Status Return Packet Description ............6-61 6-33 Sparse Window Read Data Return Packet Description ..........6-62 6-34 Dense Window Read Data Return Packet Description ..........6-63 6-35 Window Write Status Return Packet Description ............
  • Page 14 7-50 STDER A, B, C, D Register Bit Definitions ............. 7-104 7-51 STDERE Register Bit Definitions ................7-105 7-52 DDRn Register Bit Definitions ................. 7-106 7-53 I/O Port-Specifc Registers ..................7-109 7-54 RMRR0-1 Register Bit Definitions ................7-111 7-55 ICCMSR Register Bit Definitions ................7-112 7-56 ICCNSE Register Bit Definitions ................

  • Page 15: Preface

    Intended Audience This manual is intended for developers of system software and for service personnel. It discusses the AlphaServer 8200/8400 systems that are de- signed around the DECchip 21164 CPU and use the TLSB bus as the main communication path between all the system modules. The manual de- scribes the operations of all components of the system: the TLSB bus, CPU modules, memory modules, and the I/O modules.
  • Page 16 Nonprivileged software cannot invoke Undefined op- erations. Documentation Titles Table 1 lists the books in the Digital AlphaServer 8200 and 8400 documen- tation set.

  • Page 17: Digital Alphaserver 8200/8400 Documentation

    Table 1 Digital AlphaServer 8200/8400 Documentation Title Order Number Hardware User Information and Installation EK–T8030–OP Operations Manual EK–T8030–SP Site Preparation Guide EK–T8230–IN AlphaServer 8200 Installation Guide AlphaServer 8400 Installation Guide EK–T8430–IN Service Information Kit QZ–00RAC–GC Service Manual (hard copy) EK–T8030–SV AK–QKNFA–CA...
  • Page 18 Table 1 Digital AlphaServer 8200/8400 Documentation (Continued) Title Order Number EK–KXMSX–IN KZMSA Adapter Installation Guide EK–RRDRX–IN RRDCD Installation Guide Upgrade Manuals: 8200 System Only EK–DWL82–IN DWLPA PCI Shelf Installation Guide EK–H7266–IN H7266 Power Regulator Installation Card EK–H7267–IN H7267 Battery Backup Installation Card...

  • Page 19: Related Documents

    AA–Q6WVA–TE StorageWorks RAID Array 200 Subsystem Family Software User’s Guide for OpenVMS AXP AA–Q6TGA–TE StorageWorks RAID Array 200 Subsystem Family Software User’s Guide for DEC OSF/1 Operating System Manuals EY–L520E–DP Alpha Architecture Reference Manual AA–PJU7A–TE DEC OSF/1 Guide to System Administration AA–PS2DE–TE...

  • Page 21: Chapter 1 Overview

    DEC 7000/10000 systems. It is built around the TLSB bus and supports the OpenVMS Alpha and Digital UNIX operat- ing systems. It is manufactured in two models: AlphaServer 8200 and Al- phaServer 8400. The AlphaServer 8400 features nine nodes, while Al- phaServer 8200 supports only five nodes.

  • Page 22: Bus Architecture

    Futurebus+, or PCI bus. The local I/O options on the integrated I/O port appear to software as a PCI bus connected to a hose. Figure 1-1 shows a block diagram of the 8400 system. Figure 1-1 AlphaServer 8400 System Block Diagram CPU, CPU, CPU,...

  • Page 23: Cpu Module

    bus transactions may be overlapped, and these transactions may be over- lapped with bus arbitration. Arbitration priority rotates in a round-robin scheme among the nodes. A node in the slot dedicated to I/O follows a spe- cial arbitration algorithm so that it cannot consume more than a certain fraction of the bus bandwidth.

  • Page 24: Backup Cache

    to the DECchip 21164 Functional Specification for a complete description of the DECchip 21164 and PALcode. 1.3.2 Backup Cache Each backup cache (B-cache) is four Mbytes in size. In a dual-processor module there are two independent backup caches, one for each CPU. Each B-cache is physically addressed, direct-mapped with a 64-byte block and fill size.

  • Page 25: I/O Architecture

    ported by a single motherboard design. The 2-Gbyte memory option uses a different motherboard and SIMM design. A maximum of seven memory modules may be configured on the TLSB (in a system with one CPU module and one I/O module). Thus, the maximum memory size is 14 Gbytes, using 2-Gbyte modules.

  • Page 26: Software

    tion to two 10BaseT Ethernet ports, one FDDI port, and three FWD and one single-ended SCSI ports. The DWLMA is the interface between a hose and a 14-slot XMI bus. It manages data transfer between XMI adapters and the I/O port. The DWLAA is the interface between a hose and a 10-slot Futurebus+ card cage.

  • Page 27: Openvms Alpha

    • KDM70 – XMI to SI disk/tape • KZMSA – XMI to SCSI disk/tape • KFMSB – XMI to DSSI disk/tape and OpenVMS clusters • CIXCD-AC – XMI to CI HSC disk/tape and OpenVMS clusters • DEMNA – XMI to Ethernet networks and OpenVMS clusters •...

  • Page 28: Loadable Diagnostic Execution Environment

    — Cache/memory exerciser — I/O port/DWLMA loopback exerciser — Disk/tape device exerciser — Network exerciser — FBE exerciser — XCT (XMI bus exerciser) exerciser • Manual tests A subset of these diagnostics is invoked at system power-up. Optionally, they may be invoked on every system boot. The subset can also be invoked by the user through console command.

  • Page 29: Chapter 2 Tlsb Bus

    4–8. These five nodes are on the back side of the centerplane. AlphaServer 8200 supports the five backplane nodes only. I/O modules are restricted to nodes 6, 7, and 8. Node 8 in both mod-...

  • Page 30: Transactions

    2.1.1 Transactions A transaction couples a commander node that issues the request and a slave node that sequences the data bus to transfer data. This rule applies to all transactions except CSR broadcast space writes. In these transac- tions, the commander is responsible for sequencing the data bus. CPUs and I/O nodes are always the commander on memory transactions and can be either the commander or the slave on CSR transactions.

  • Page 31: Tlsb Signal List

    The TLSB implements parity checking on all address and command fields on the address bus, ECC protection on the data field, and protocol se- quence checking on the control signals across both buses. 2.1.5 TLSB Signal List Table 2-1 lists the signals on the TLSB. Signal name, function, and de- fault state are given.
  • Page 32 Table 2-1 TLSB Bus Signals (Continued) Default Signal Name State Function TLSB_PS_TX L Power supply transmit status Expander select TLSB_EXP_SEL<1:0> L Secure console TLSB_SECURE L Local disk converter LDC_PWR_OK L I/O unit A power OK PIU_A_OK L PIU_B_OK L I/O unit B power OK System run indicator TLSB_RUN L Console win status...

  • Page 33: Operation

    8. Table 2-2 identifies the nodes on the TLSB. The AlphaServer 8200 has nodes 4 to 8 only. Node 4 must be a CPU mod- ule. Node 8 is dedicated to an I/O module.

  • Page 34: Virtual Node Identification

    2.2.2 Virtual Node Identification TLSB system operation requires that certain functional units can be iden- tified uniquely, independent of their physical location. Specifically, individ- ual memory banks and CPUs must be uniquely addressable entities at the system level. As multiple memory banks and CPUs are implemented on single modules, a physical node ID is insufficient to uniquely address each bank or each CPU.

  • Page 35: Tlsb Memory Address Bit Mapping

    drive the address and command, the outcome of the tag lookup can be evaluated by the bus interface. If the lookup is a hit, then the CPU bus interface nulls the TLSB command field and cancels the request. Although this consumes potentially needed address bus slots, the address bus re- quires two cycles to initiate a command and the data bus requires three cy- cles per transaction.

  • Page 36: Memory Bank Addressing Scheme

    2.2.3.1 Memory Bank Addressing Scheme The TLSB supports one terabyte of physical memory. The memory ad- dress space is accessed by a 40-bit byte address. The granularity of ac- cesses on the TLSB is a 64-byte cache block. I/O adapters that need to ma- nipulate data on boundaries less than 64 bytes require the commander node to perform an atomic Read-Modify-Write transaction.

  • Page 37: Memory Bank Address Decoding

    2.2.3.3 Memory Bank Address Decoding The minimum bank size for the TLSB address decode scheme is 64 Mbytes. To address memory, a CPU or I/O node must perform a memory bank de- code to test the status of the bank. The memory modules transmit the status of each bank on the 16 TLSB_BANK_AVL lines.

  • Page 38: Address Decode

    Figure 2-2 Address Decode Physical Address ADRMASK ADDRESS Decode and Mask Decode and Mask Compare 0 10 Address Hit PHAdr INTMASK INTLV Mask Mask Compare Valid Interleave Hit Bank Hit BXB0830.AI When a physical address is presented to the bank decode logic, all valid ad- dress bits, as determined by the ADRMASK field, are compared with their corresponding physical address bits.

  • Page 39: Bank Available Status

    2.2.3.4 Bank Available Status TLSB_BANK_AVL indicates that a bank is available for use. When not asserted, no requests except Write Bank Unlock can be issued to that bank. Each memory bank has one of the TLSB_BANK_AVL<15:0> signals as- signed to it by the console. The number of the TLSB_BANK_AVL bit corre- sponds to the bank number assigned to that bank.

  • Page 40: Address Bus Arbitration

    2.2.4 Address Bus Arbitration The TLSB bus has demultiplexed address and data buses. These buses op- erate independently and are related only in as much as a valid command on the address bus will result in a data transfer on the data bus at some later time.

  • Page 41: Address Bus Request

    Consequently, the priority of any device will eventually bubble up to the highest level. The no-op command is the only non-data transfer command; it does not affect priorities. TLSB_REQ8_HIGH and TLSB_REQ8_LOW are assigned to the I/O mod- ule in node 8. These lines represent the highest and the lowest arbitration priorities.

  • Page 42: False Arbitration Effect On Priority

    in a request cycle, that CPU must take part in the following arbitration cy- cle even if the bus is no longer required. If the device wins the bus, it as- serts a no-op on the bus command lines. I/O devices in the dedicated I/O port node cannot use early arbitration. 2.2.4.9 False Arbitration Effect on Priority Relative bus priorities are only updated when a data transfer command is...

  • Page 43: Bank Collision

    CPUs can request the bus without first checking that the bank is busy. If the bank does turn out to be busy, this is considered a false arbitration, and the command is a no-op. The device can request the bus again when the bank is free.

  • Page 44: Command Acknowledge

    in subsequent CSR accesses, and it is not ready to source or accept data, it can delay asserting TLSB_SEND_DATA, or it can assert TLSB_HOLD on the bus. 2.2.4.15 Command Acknowledge When a device asserts an address, bank number, and a valid data transfer command on the bus, the targeted device responds two cycles later by as- serting TLSB_CMD_ACK.

  • Page 45: Address Bus Commands

    • No-op command cycles Two signals are used to provide parity protection on the address bus dur- ing all command cycles. TLSB_CMD_PAR is asserted to generate odd par- ity for the signals TLSB_CMD<2:0>, TLSB_BANK_NUM<3:0>, TLSB_ADR<39:31>, and TLSB_ADR<4:3>. TLSB_ADR_PAR is asserted to generate odd parity for the signals TLSB_ADR<30:5>.

  • Page 46: Data Bus Concepts

    Write Bank Unlock Used by the I/O port to complete a Read-Modify-Write. Writes the data specified by the address and bank number and unlocks the bank. CSR Read Read the CSR location specified by the address. Bank number specifies a CPU virtual ID.

  • Page 47: Back-To-Back Return Data

    2.2.7.3 Back-to-Back Return Data Two memory read transactions are returned back to back as follows. TLSB_SEND_DATA for the first transaction is asserted, and the shared and dirty state is driven to the bus. Three cycles after the first TLSB_SEND_DATA assertion, the second memory initiates its transfer. The two transfers proceed normally, piped three cycles apart.

  • Page 48: Sequence Numbers

    If one CPU drives TLSB_HOLD while another drives TLSB_SHARED or TLSB_DIRTY, the second keeps driving TLSB_SHARED and TLSB_DIRTY. TLSB_HOLD, TLSB_SHARED, and TLSB_DIRTY are as- serted for one cycle and deasserted in the next cycle. This two-cycle se- quence repeats until TLSB_HOLD is not reasserted (the no-Hold cycle). Receivers internally convert TLSB_HOLD to appear asserted in both cy- cles.

  • Page 49: Ecc Coding

    Table 2-5 TLSB Data Wrapping TLSB_ADR<5> Data Cycle Data Bytes 0–31 32–63 32–63 0–31 2.2.8.6 ECC Coding Data is protected using quadword ECC. The 256-bit data bus is divided into four quadwords. Protection is allocated as follows: • TLSB_D<63:0> is protected by TLSB_ECC<7:0> •...

  • Page 50: Ecc Error Handling

    Check bits are computed by XORing all data bits corresponding to columns containing a one in the upper table and inverting bits <3:2>. These check bits are transmitted on the TLSB_ECC lines. An error syndrome is computed by XORing all data and check bits corre- sponding to columns containing a one in both tables and inverting bits <3:2>.

  • Page 51: Tlsb_Dirty

    TLSB_SHARED is valid when driven in response to Read, Read Bank Lock, Write, and Write Bank Unlock commands. Nodes may, therefore, drive TLSB_SHARED in response to any command; the value of TLSB_SHARED is only guaranteed to be accurate when TLSB_SHARED is asserted in response to the commands named above.

  • Page 52: Miscellaneous Bus Signals

    2.2.9 Miscellaneous Bus Signals Several signals are required for correct system operation. They are: • TLSB_DATA_ERROR — A hard or soft data error has occurred on the data bus. • TLSB_FAULT — A system fatal event has occurred. • TLSB_RESET — Reset the system and initialize. •...

  • Page 53: Csr Addressing

    and allows the CPUs asserting TLSB_LOCKOUT to complete their bus ac- cess without interference. TLSB_LOCKOUT is asserted for one cycle then deasserted for one cycle. This two-cycle sequence may be repeated until the device is ready to deassert TLSB_LOCKOUT. Multiple devices may assert this signal in any of these two-cycle sequences.

  • Page 54: Csr Address Space Regions

    Figure 2-4 TLSB CSR Address Bit Mapping Processor Byte Address Address CSR Address Field BXB0827.AI 2.3.1 CSR Address Space Regions A total of 1 terabyte of physical address space can be mapped directly to the TLSB. Physical address bit <39> normally indicates an I/O space ref- erence from the CPU, so the first 512 Gbytes are reserved, and all address bits can be mapped directly to the TLSB address bus.

  • Page 55: Tlsb Csr Space Map

    Figure 2-5 TLSB CSR Space Map Byte Address F0 0000 0000 Reserved FF 87FF FFC0 FF 8800 0000 Node 0 CSRs: 64K CSR Locations FF 883F FFC0 FF 8840 0000 Node 1 CSRs: 64K CSR Locations FF 887F FFC0 ..

  • Page 56: Tlsb Node Base Addresses

    Table 2-7 TLSB Node Base Addresses Node Number BB Address <39:0> Module FF 8800 0000 CPU, Memory FF 8840 0000 CPU, Memory FF 8880 0000 CPU, Memory FF 88C0 0000 CPU, Memory FF 8900 0000 CPU, Memory, I/O FF 8940 0000 CPU, Memory, I/O FF 8980 0000 CPU, Memory, I/O...

  • Page 57: Tlsb Csr Address Mapping

    Table 2-8 TLSB CSR Address Mapping Modules That Address Name Mnemonic Implement BB+000 Device Register TLDEV CPU, Memory, I/O Bus Error Register TLBER CPU, Memory, I/O BB+040 Configuration Register TLCNR CPU, Memory, I/O BB+080 Virtual ID Register TLVID CPU, Memory BB+0C0 Memory Mapping Register TLMMR0...

  • Page 58: Tlsb Mailboxes

    2.3.2 TLSB Mailboxes CSRs that exist on external I/O buses connected to an I/O port (or another I/O module implementing mailbox register access) are accessed through mailbox structures that exist in main memory. Read requests are posted in mailboxes, and data and status are returned in the mailbox. Mailboxes are allocated and managed by operating system software (successive op- erations must not overwrite data that is still in use).
  • Page 59 Table 2-9 describes the mailbox data structure. Table 2-9 Mailbox Data Structure Bit(s) Name Description <29:0> Remote Bus Command. Controls the remote bus opera- tion and can include fields such as address only, address width, and data width. See Alpha SRM. <30>...

  • Page 60: Window Space I/O

    structure. Software may choose to reuse mailboxes (for example, multiple reads from the same CSR), or it may maintain templates that are copied to the mailbox. Byte masks may be needed by some hardware devices for correct operation of a CSR read as well as a CSR write. A bit is set in the mailbox MASK field to disable the corresponding byte location to be read or written.

  • Page 61: Tlsb Errors

    predictable as the value has no significance. The I/O node may choose not to acknowledge the command and save data bus cycles. The I/O node proceeds to read the selected remote CSR. When the data is available and there are no errors reading the data, the I/O node issues a CSR write command to a CSR Read Data Return Data (TLRDRD) Register in local CSR broadcast space.

  • Page 62: Error Categories

    2.4.1 Error Categories Error occurrences can be categorized into four groups: • Hardware recovered soft errors • Software recovered soft errors • Hard errors • System fatal errors 2.4.1.1 Hardware Recovered Soft Errors Soft errors of this class are recoverable and the system continues opera- tion.

  • Page 63: Error Signals

    2.4.2 Error Signals The TLSB provides two signals for broadcasting the detection of an error to other nodes. All nodes monitor the error signals, TLSB_DATA_ERROR and TLSB_FAULT (Section 2.2.9) , to latch status relative to the error. Except for system fatal errors, only the commander (CPU or I/O node) checks whether a command completes with or without errors.

  • Page 64: Command Field Parity Errors

    every cycle, enabled solely by the driven assertion value. For example, TLSB_CMD_ACK is assertion checked to verify that if this node at- tempts to assert it, the signal is received asserted. If this node is not asserting TLSB_CMD_ACK, possibly some other node is asserting it. The following fields are level-checked only when the commander has won the bus and is asserting a command and address: •...

  • Page 65: Unexpected Acknowledge

    When a commander node issues a CSR access command but does not re- ceive acknowledgment, it sets <NAE> in the TLBER register. Only the commander that issues the command detects this error and sets <NAE>. The error is not broadcast and handling is node specific. The exception to this rule is a CSR write to a Mailbox Pointer Register;...

  • Page 66: Memory Mapping Register Error

    BER<BAE> is set if the Write Bank Unlock command appears on the bus before the second data cycle of the preceding Read Bank Lock command. If any node receives a CSR access command (to any address) while a CSR command is in progress, the node sets TLBER<BAE> and asserts TLSB_FAULT six cycles after the command.

  • Page 67: Data Bus Errors

    Table 2-10 Address Bus Error Summary Error Description Who Detects Signal Address Transmit Check Error Commander TLSB_FAULT ATCE Address Parity Error TLSB_FAULT Bank Busy Violation Error TLSB_FAULT Bank Lock Timeout Memory None LKTO No Acknowledge to CSR Access Commander None No Acknowledge to Memory Access Commander TLSB_FAULT...

  • Page 68: Single-Bit Ecc Errors

    2.4.4.1 Single-Bit ECC Errors A single-bit error on a memory data transfer is detected by a node’s ECC checking logic. The decision to correct the data or not is implementation specific. If a node detects a single-bit ECC error, it logs the error in the TLESRn register by setting either <CRECC>...

  • Page 69: Data Status Errors

    This timeout can be disabled by software. The <DTOD> bit in the TLCNR register prevents <DTO> from setting. It does not clear <DTO> if already set. 2.4.4.5 Data Status Errors The TLSB_STATCHK signal is used as a check on TLSB_SHARED and TLSB_DIRTY.

  • Page 70: Summary Of Data Bus Errors

    System fatal data bus errors are cumulative. Should a second system fatal error occur, TLSB_FAULT is asserted a second time. If a fatal error is of a different type than the first, an additional error is set in the TLBER regis- ter.

  • Page 71: Error Recovery

    Some errors are more important to software than others. For example, should two correctable data errors occur, one during a write to memory and the other during a read from memory, the error during the write would be more important. The software can do no more than log the read error as it should be corrected by hardware.
  • Page 72 The CSR registers contain information about the error. The commander’s TLBER register contains either correctable or uncorrectable error status, and the TLFADRn registers contain the command code, bank number, and possibly the address. If TLSB_DATA_ERROR asserted, the node that transmitted the data will have set the <DTDE>. If <DTDE> is set in a memory node, there were only two nodes involved in the data transfer.

  • Page 73: Write Errors

    2.4.6.2 Write Errors Write data operations involve a minimum of two nodes. The commander issues the command and transmits the data. A memory node acknowl- edges as the slave, provides the timing for the data transaction, and re- ceives the data. All other nodes check to see if their cache is sharing the data and may assert TLSB_SHARED.
  • Page 74 still cause interrupts. Interrupts for correctable read data errors should also be disabled, as read errors will result from not correcting the single- bit errors in data that gets written into memory. Disabling correctable write data errors involves setting <CWDD> in the TLCNR register of all nodes in the system.

  • Page 75: Chapter 3 Cpu Module

    Chapter 3 CPU Module The CPU module is a DECchip 21164 based dual-processor CPU module. Each CPU chip has a dedicated 4-Mbyte module-level cache (B-cache) and a shared interface to memory and I/O devices through the TLSB bus. 3.1 Major Components The major components of the CPU module are: •...

  • Page 76: Decchip 21164 Processor

    The DECchip 21164 microprocessor is a CMOS-5 (0.5 micron) superscalar, superpipelined implementation of the Alpha architecture. DECchip 21164 features: • Alpha instructions to support byte, word, longword, quadword, DEC F_floating, G_floating, and IEEE S_floating and T_floating data types. It provides limited support for DEC D_floating operations.

  • Page 77: Mmg

    • On-chip 8-Kbyte virtual instruction cache with seven-bit ASNs (MAX_ASN=127). • On-chip dual-read-ported 8-Kbyte data cache (implemented as two 8- Kbyte data caches containing identical data). • On-chip write buffer with six 32-bit entries. • On-chip 96-Kbyte 3-way set associative writeback second-level cache. •...

  • Page 78: B-Cache

    To facilitate the multiplexing of the 256 bits of TLSB data to the 128 bits required by the DECchip 21164 interface, longwords (0,4), (1,5), (2,6) and (3,7) are paired together. This pairing is achieved by "criss-crossing" the signals coming from the TLSB connector to the DIGA pins. The DIGA transfers CSR data to/from the ADG and data path.

  • Page 79: Serial Rom Port

    • A set of module-level parallel I/O ports for functions such as LED status indicators and node identification • Two serial I/O ports connected to the serial ROM I/O of the DECchip 21164’s for manufacturing diagnostic use • Support for serial number loading Communications to the UARTs, FEPROMs, watch chip, LED control regis- ters, and other registers are accomplished over the 8-bit wide Gbus.

  • Page 80: Cpu Module Address Space

    Table 3-1 Directly Addressable Console Hardware Console Hardware Address FF 9000 0000 - FF 93FF FFC0 FEPROM FF 9400 0000 - FF 97FF FFC0 FEPROM FF 9800 0000 - FF 9BFF FFC0 Reserved FF 9C00 0000 - FF 9FFF FFC0 Reserved UART chip FF A000 0000 - FF A100 00C0...

  • Page 81: Memory Space

    from cache or the TLSB as shown in Table 3-2. Bit <4> specifies which 16-byte portion of the 32-byte subblock is returned first from the DIGA or cache. Bits <3:0> specify the byte being accessed. Table 3-2 TLSB Wrapping TLSB_ADR<5> Data Return Order Data returned in order Data Cycle 0 ->...

  • Page 82: I/O Space

    3.3.2 I/O Space The I/O space contains the I/O window space, TLSB CSR space, module Gbus space, and DECchip 21164 private CSR space. It is selected when bit <39> is one. 3.3.2.1 I/O Window Space This space, defined by addresses in the range 80 0000 0000 to DF FFFF FFC0 is used for PCI bus addressing.

  • Page 83: Gbus Space

    3.3.2.3 Gbus Space The Gbus is the collective term for the FEPROMs, console UARTs, watch chip, and module registers. All Gbus registers are 1-byte wide, addressed on 64-bytes boundaries. Figure 3-4 shows how local Gbus space registers are assigned. Figure 3-4 Gbus Map Byte Address FF 9000 0000...

  • Page 84: Cpu Module Window Space Support

    3.4 CPU Module Window Space Support CSRs that exist on some external I/O buses are accessed through window space transactions. Rather than issuing a read command and waiting for data to be returned to the CPU module from an external I/O bus, the CPU module and I/O port have a protocol to permit disconnected reads.

  • Page 85: Pci Accesses

    Table 3-4 Decrement Queue Counter Address Assignments I/O Port Slot Address Designation BSB+400 TLWSDQR4 - Window Space DECR Queue Counter for slot 4 BSB+440 TLWSDQR5 - Window Space DECR Queue Counter for slot 5 BSB+480 TLWSDQR6 - Window Space DECR Queue Counter for slot 6 BSB+4C0 TLWSDQR7 - Window Space DECR Queue Counter for slot 7 BSB+500...

  • Page 86: Sparse Space Reads And Writes

    Table 3-5 PCI Address Bit Descriptions Name Bit(s) Function IO_SPACE <39> DECchip 21164 I/O space if set to 1. <38:36> Selects address space as follows: IOP_SEL Bits <38:36> Selected Space Node 4 Node 5 Node 6 Node 7 Node 8 Selects hose number on that module <35:34>...

  • Page 87: Dense Space Reads And Writes

    data issued by DECchip 21164 is transmitted on the TLSB, along with all the INT4 mask bits. The I/O port pulls the appropriate longword out of the 32-byte block and packages it, along with address bits <4:3>, into a Down Hose packet.

  • Page 88: Cpu Module Errors

    Dense PCI memory space is longword addressable only. You cannot write to individual bytes. You must do longword writes. You can do quadword writes using the STQ instructions, if you want. To get at individual bytes, you must use the sparse space access method. Writes to dense PCI memory space will be merged up to 32 bytes and per- formed in one PCI transaction to the extent that the PCI target device can deal with writes of this size.

  • Page 89: Faults

    are reported to DECchip 21164 through system machine check interrupts (IPL 1F hex - SYS_MCH_CHK_IRQ). The interrupt causes the DECchip 21164 to vector to the SCB system machine check entry point (offset 660 hex) when DECchip 21164’s IPL drops below 1F hex and DECchip 21164 is not in PAL mode.

  • Page 90: Nonacknowledged Csr Reads

    • Data Timeout Error (DTO) • Data Status Error (DSE) • Sequence Error (SEQE) • Data Control Transmit Check Error (DCTCE) • Address Bus Transmit Check Error (ABTCE) • Unexpected Acknowledge Error (UACKE) • Memory Mapping Register Error (MMRE) • Bank Busy Error (BBE) •...

  • Page 91: Transmit Check Errors

    3.5.2.1 Transmit Check Errors A node must check that its bus assertions get onto the bus properly by reading from the bus and comparing it to what was driven. A mismatch can occur because of a hardware error on the bus, or if two nodes attempt to drive the fields in the same cycle.

  • Page 92: No Acknowledge Errors

    3.5.2.3 No Acknowledge Errors Whenever a commander node expects but does not receive an acknowledg- ment of its address transmission as an assertion of TLSB_CMD_ACK, it sets an error bit in its TLBER register. For memory space accesses that are not acknowledged, <FNAE> is set: for CSR accesses, <NAE> is set. The exception to this rule is a CSR write to I/O mailbox registers;...

  • Page 93: Multiple Errors

    3.5.4 Multiple Errors The error registers can only hold information relative to one error. It is the responsibility of software to read and clear all error bits and status. Even when errors occur infrequently there is a chance that a second error can occur before software clears all status from a previous error.

  • Page 95: Chapter 4 Memory Subsystem

    Chapter 4 Memory Subsystem The memory subsystem consists of hierarchically accessed levels that re- side in different locations in the system. The memory hierarchy consists of three main parts: • Internal Caches - These caches reside on the DECchip 21164. •...

  • Page 96: Second-Level Cache

    4.1.3 Second-Level Cache The second-level cache (S-cache) is a 96-Kbyte, 3-way set associative, physically addressed, write-back, write-allocate cache with 32- or 64-byte blocks (configured by SC_CTL<SC_BLK_SIZE>; see DECchip 21164 Func- tional Specification). It is a mixed data and instruction cache. The S- cache is fully pipelined.

  • Page 97: B-Cache Tags

    4.2.2 B-Cache Tags Many locations in memory space can map onto one index in the cache. To identify which of these memory locations is currently stored in the B-cache, a tag for each block is stored in the tag address RAMs. This tag together with the B-cache index uniquely identifies the stored block.

  • Page 98: Updates And Invalidates

    Figure 4-3 Cache Index and Tag Mapping to Block Address (16MB) Processor Byte Address Tag<38:24> B-Cache Index<23:6> Wrap Order BXB0822.AI 4.2.3 Updates and Invalidates If a block is shared, and a CPU wants to write it, the write must be issued on the TLSB.

  • Page 99: B-Cache State Changes

    Table 4-1 B-Cache States B-Stat State of Cache Line Assuming Tag Match Cache miss. The block is not present in the cache. Valid for read or write. This cache line contains the only cached copy of the block. The copy in memory is identical to this block. Valid for read or write.

  • Page 100: Victim Buffers

    • State transition due to TLSB activity Table 4-3 shows how the cache state can change due to bus activity. TLSB writes always clean (make nondirty) the cache line in both the initiating node and all nodes that choose to take the update. They also update the appropriate location in main memory.

  • Page 101: State Transition Due To Processor Activity

    Table 4-2 State Transition Due to Processor Activity Processor TLSB Next Cache Request Tag Probe Result Action on TLSB Response State ______ ______ _____ Invalid Read Shared Shared, Dirty Read _____ Invalid Read Shared Shared, Dirty Read ______ ______ Invalid Read Shared Shared, Dirty...

  • Page 102: Cache Coherency On Processor Writes

    Table 4-3 State Transition Due to TLSB Activity TLSB Module Next Cache Operation Tag Probe Result Response State Comment _____ ______ _____ Match OR Invalid Shared, Dirty No change Read _____ ______ _____ Match OR Invalid Shared, Dirty No change Write _____ _____...

  • Page 103: Memory Barriers

    the write must be reissued by the DECchip 21164 to the TLSB as a Write Block. In the case that the Set Dirty bit is held off by an invalidate to the block, the Set Dirty request is reissued as a Read-Miss-Modify. To perform a write to a shared block, DECchip 21164 issues a Write Block request.

  • Page 104: Major Sections

    During memory writes, TLSB memory modules store write data and ECC check bits as they are received off the TLSB. A minor modification of the ECC check bits is done before they are written to the DRAMs to allow for the addition of a row parity bit and a column parity bit to provide addi- tional data integrity protection.

  • Page 105: Control Address Interface

    4.3.1.1 Control Address Interface The control address interface (CTL) is a single gate array. It provides the interface to the TLSB, controls DRAM timing and refresh, runs memory self-test, and contains some of the TLSB and memory-specific registers. CTL decodes the TLSB command and memory bank in the case of memory reads and writes, or the TLSB address during CSR operations to deter- mine if it is selected for this transaction.

  • Page 106: Dram Arrays

    DRAM arrays. The MDI includes data buffers, ECC checking logic, self- test data generation and checking logic, and CSRs. MDI concatenates two 72-bit TLSB transfers into one 144-bit transfer to the DRAMs during memory writes. During memory reads, 144-bit reads from the DRAMs are issued onto the TLSB via two 72-bit consecutive transfers.

  • Page 107: Memory Organization

    four memory modules, with at least two strings each, supports a maximum of 8-way interleaving. 4.3.2 Memory Organization The physical memory composed of a single or multiple memory modules can be organized in various ways to optimize memory access. Memory can be configured with MS7CC modules of various capacities, from 128 Mbytes to 2 Gbytes.

  • Page 108: Two-Way Interleave Of A 128-Mbyte Dram Array

    Figure 4-5 Two-Way Interleave of a 128-Mbyte DRAM Array Bank 0 Bank 1 0000 0000 0000 0040 0000 0080 0000 00C0 64 Mbytes 64 Mbytes 07FF FF80 07FF FFC0 Block size = 64 Bytes DRAM size 4 Mbits Memory Capacity = 128 Mbytes BXB-0307A-92 Memory modules of different capacities can be interleaved as a set with modules of another capacity.

  • Page 109: Eight-Way System Interleave Of Four 128-Mbyte Memory Modules

    module can result in reduced system throughput due to common data path contention between the two banks. At the module level, the DRAM arrays can be interleaved on 64-byte block boundaries. The DRAM array in a 2-string MS7CC memory module is al- ways interleaved.

  • Page 110: Refresh

    group of DRAM arrays. The default mode optimizes interleaving of mem- ory in any arrangement of memory modules. If the FEPROM specifies explicit interleave sets, the console then inter- leaves the arrays as requested. In a noninterleave mode, the console con- figures arrays in order, by node number, with the lowest numbered array at the lowest physical address.

  • Page 111: Self-Test Modes

    sole to locate and map out bad areas of physical address space. Self-test is invoked during system power-up, when a TLSB reset occurs, or by writing to the appropriate CSRs. Two versions of self-test are supported. A normal self-test that runs upon power-up/reset and tests the module rapidly and completely with "pseudo- random"...

  • Page 112: Self-Test Error Reporting

    To exercise the array at its maximum operating speed, banks 0 and 1 are always interleaved during self-test if the module contains more than one string of DRAMs. NOTE: Bank 0 contains the even numbered strings; Bank 1 contains the odd num- bered strings.

  • Page 113: Self-Test Performance

    NOTE: Successful execution is not a measure of the array integrity. It indicates that every location in memory space has been tested and written with good or bad ECC. If node reset occurs during self-test, the array will be left in an unknown state.

  • Page 114: Self-Test Times: Moving Inversion, No Errors Found

    Table 4-8 Self-Test Times: Moving Inversion, No Errors Found Module Capacity Test Time (minutes) (Mbytes) 4 Mbit DRAM 16 Mbit DRAM 1024 10.6 2048 1 NA = Not applicable 4-20 Memory Subsystem...

  • Page 115: Chapter 5 Memory Interface

    Chapter 5 Memory Interface The memory interface to the TLSB consists of three parts: • Control address interface • Memory data interface • CSR interface 5.1 Control Address Interface The control address interface (CTL) is the primary controller chip for the TLSB memory.

  • Page 116: Memory Bank State Machine

    5.1.1.1 Memory Bank State Machine The CTL contains two TLSB control state machines, one for each memory bank. The state machines receive/generate information from/to the TLSB bus as well as other TLSB support logic and DRAM control logic. Each state machine begins operation when a valid TLSB transaction request destined for the particular memory bank that it supports is received.

  • Page 117: Tlsb Bank Match Logic

    command is one of the factors in determining if the command is acknowl- edged (TLSB_CMD_ACK) by this node. Table 5-1 shows the encoding of TLSB commands. Table 5-1 TLSB Command Encoding Command Code Description No operation No-op Victim eviction (as memory write) Victim Memory read Read...

  • Page 118: Tlsb Bank Available Flags

    received from the TLSB bus. TLSB_SEND_DATA is also used to check for proper bus sequencing. Note that the TLSB_CMD_ACK and TLSB_SEND _DATA may be issued simultaneously for write transactions by the mem- ory module on an idle TLSB bus. The CTL maintains sequence number registers for each memory bank as well as for CSR transactions.

  • Page 119: Address/Ras Decode Logic

    • Write • Refresh The TLSB memory is designed to operate within the following TLSB clock cycle times: • 10.0 to 11.299 ns • 11.3 to 12.999 ns • 13.0 to 15.0 ns (Memory can operate at cycle times as slow as 30 ns us- ing power-up default settings without violating the DRAM refresh re- quirements.) To support operating at multiple cycle times while maintaining low latency...

  • Page 120: 256Mb/1024Mb Memory Module Addressing

    Table 5-2 Two Strings—128MB/512MB Row/Column Address Bit Swapping DRAM Type 4 Mbit 16 Mbit No. of Banks Interleaved DRAM Address Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> x(21) x(21) x(21) x(21) x(22) x(22) x(22) x(22) Row_Adr<0> Col_Adr<0>...

  • Page 121: 512Mb/2048Mb Memory Module Addressing

    Table 5-3 Four Strings—256MB/1024MB Row/Column Address Bit Swapping DRAM Type 4 Mbit 16 Mbit No. of Banks Interleaved DRAM Address Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> x(21) x(21) x(21) x(21) x(22) x(22) x(22) x(22) Row_Adr<0> Col_Adr<0>...

  • Page 122: Eight Strings-512Mb/2048Mb Row/Column Address Bit Swapping

    Table 5-4 Eight Strings—512MB/2048MB Row/Column Address Bit Swapping DRAM Type 4 Mbit 16 Mbit No. of Banks Interleaved DRAM Address Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> Row_Adr<0> x(21) x(21) x(21) x(21) Row_Adr<0> Row_Adr<0> x(22) x(22) x(22) x(22) Col_Adr<0>...

  • Page 123: Memory Data Interface

    5.2 Memory Data Interface The memory data interface (MDI) is comprised of four chips connected to the DRAM array on one side and to the TLSB bus on the other. The MDI contains the following logic elements: • Data path logic •...

  • Page 124: Csr Write Data Ecc Check

    Figure 5-1 64-Bit ECC Coding Scheme 3322 2222 2222 DATA 6666 5555 5555 5544 4444 4444 3333 3333 1111 1111 BITS 3210 9876 5432 1098 7654 3210 9786 5432 1098 7654 3210 9876 5432 1098 7654 3210 1111 1111 0000 XOR S7 0000 0000...

  • Page 125: Write Data Out Selection

    5.2.2.5 Write Data Out Selection A 2:1 multipexer and a tristate enable capability are provided for interfac- ing the write data buffers to the DRAM array bus. The multiplexer allows the selection of data from either the bank 0 or the bank 1 buffers. The tri- state enable capability allows the write data output to the DRAM array bus to be disabled so that it may be used for receiving read data.

  • Page 126: Mdi Error Detection And Correction Logic

    on all CSR reads from memory. The ECC bits are generated across bits <63:0> and transmitted on TLSB_ECC<7:0>. 5.2.4 MDI Error Detection and Correction Logic The four MDIs monitor the data received from the TLSB for write data er- rors. They also monitor read data for ECC errors after it has been trans- mitted onto the TLSB.

  • Page 127: Csr Interface

    in these bits. This field is undefined when either CRECC, CWECC, or ECC is zero. 5.3 CSR Interface The CSR interface, used to transfer the appropriate CSR information be- tween the CTL and the four MDI chips consists of an 8-bit data bus with parity and a command timing signal.

  • Page 128: Tlsb Csr Control

    • Multiplexing of local CTL CSRs and the data bytes within them • Byte-wide parity generation and checking of the CSRCA bus 5.3.1.1 TLSB CSR Control The TLSB CSR control monitors the TLSB bus for either a CSR read or a CSR write command destined for that particular node.

  • Page 129: Mai Csr Sequencer

    The memory adapter supports TLSB broadcast writes to its MCR register at address location BSB+1880 (byte address). This allows for the DRAM timing rates, accessed through the MCR register to be written simultane- ously, thereby ensuring simultaneous refresh of all memory modules. Since the commander initiating the broadcast write issues both the TLSB_CMD_ACK and TLSB_SEND_DATA for the transaction, this is the only transaction for which the memory adapter may issue TLSB_HOLD.

  • Page 130: Csr Multiplexing

    onto the CSRCA bus during a read of one of its internal CSRs. During a write command to one of the CTL’s CSRs, a LD_EN signal from the se- quencer is used to enable data from the CSRCA bus into the proper CSR. Note that the LD_EN signal occurs on the last cycle of each of the four data byte transfers.

  • Page 131: Merge Register

    Table 5-7 CSRCA Data Bus Master Chip Select Read/Write CSRCA Driver Read 1XX - CTL Read MD13 011 - MDI3 Read MD12 010 - MDI2 Read MD11 001 - MDI1 000 - MDI0 Read MD10 Write MD10 1XX - CTL Write MD10 011 - MDI3...

  • Page 132: Csrca Parity

    5.3.2.4 CSRCA Parity The CSRCA bus is protected by byte-wide odd parity. All data transmitted over this bus is accompanied by a valid parity bit (CSRCA<8>) to be checked against the data by all chips. Parity errors on the CSRCA bus during CSR read transactions cause Unpredictable data to be returned to the TLSB bus.

  • Page 133: Chapter 6 I/O Port

    Chapter 6 I/O Port The I/O port is the interface of the I/O subsystem to the TLSB bus. Two modules can be used for I/O operations: KFTHA and KFTIA (integrated I/O port). Figure 6-1 shows the I/O subsystem block diagram with a KFTHA module.

  • Page 134: Configuration

    The I/O port interfaces the TLSB bus to up to four different I/O buses through separate I/O bus adapter modules. Digital provides three types of I/O adapters: • XMI bus adapter—DWLMA • Futurebus+ adapter—DWLAA • PCI bus adapter—DWLPA (EISA bus through a bridge on the PCI bus) 6.1 Configuration Node 8 of the TLSB is dedicated to the I/O port.

  • Page 135: I/O Port Transactions

    The two Up Hose HDRs receive packets from the four Up Hoses (two hoses per HDR) and transmit them to the IDRs through the Turbo Vortex bus. The other two Down Hose HDRs receive packets from the IDRs through the Turbo Vortex bus and transmit them to the four Down Hoses (two hoses per HDR).
  • Page 136 mation between the TLSB and I/O adapter modules by transmitting and receiving packets across the hose(s). Mailbox, I/O window, device inter- rupt, DMA read/IREAD, and NVRAM write transactions (see following subsections) consist of packet pairs: a command packet and a status re- turn packet.

  • Page 137: Mailbox Transactions

    Table 6-1 I/O Port Transaction Types Transaction Initiator TLSB Commands Hose Packets CSR read None - local I/O port registers CSR read CSR write None - local I/O port registers CSR write CSR read, CSR write Window read cmd, win rd data ret Window read Window write CSR write...
  • Page 138 The I/O port can support up to 16 CPU chips. However, if more than four CPU chips are present, any additional CPU chip must share a TLMBPR register pair with another CPU chip. CAUTION: If two CPUs are sharing a common TLMBPR, there is a slight possibility that one of the CPUs could continually win access to that TLMBPR, thus causing the other CPU to be locked out of ever gaining access to it.

  • Page 139: I/O Window Space Transactions

    6.3.2 I/O Window Space Transactions CSRs that exist on some external I/O buses are accessed through I/O win- dow space transactions. One such external I/O bus is the PCI. NOTE: Refer to the DWLPA PCI Adapter Technical Manual for further discus- sion of transactions on the PCI bus and addressing of PCI devices.

  • Page 140: Csr Read Transactions To I/O Window Space

    As soon as the I/O port empties the window read command packet from its internal buffer, it issues a CSR write command to the Window Space Dec- rement Queue Counter Register (TLWSDQRn) in CSR broadcast space. The I/O port does not ACK the write broadcast transaction nor does it gen- erate the associated data cycles.

  • Page 141: I/O Port Generated Error Interrupts

    Therefore, when an interrupt occurs on an I/O bus (that is, XMI, Future- bus+, or PCI), the I/O bus adapter must first acquire the interrupt vector for that interrupt. On the Futurebus+ and the PCI, the vector is acquired as part of the INTR transaction. On the XMI bus, the vector is acquired using an IDENT transaction.

  • Page 142: Dma Read Transactions

    • I/O port generated error interrupts transmit a special vector on the TLSB, which must be preloaded by system software into the I/O port Interrupt Vector Register (TIVR) at system initialization. • The I/O port has a special I/O port interrupt mask bit, <INTR_NSES>, that must be loaded by software at system initialization.

  • Page 143: Dma Write Transactions

    DMA IREAD command, the XMI I/O adapter acknowledges the IREAD and pends the transaction. This frees the XMI for other bus traffic. The XMI I/O adapter then transmits a quadword-aligned DMA IREAD request packet to the I/O port on the Up Hose. Included in the DMA IREAD re- quest packet is the target TLSB address, a tag field to allow the XMI I/O adapter to associate the DMA IREAD request with the DMA return data packet, and the length code indicating the amount of data requested.

  • Page 144: Dma Unmasked Write

    requires a single TLSB bus write transaction and is always a double hexword. A DMA write request packet is executed as a disconnected (write-and-run) operation and therefore has no status return packet associated with it. Once the I/O bus adapter transmits the DMA write request packet over the Up Hose, the transaction is complete.

  • Page 145: Extended Nvram Write Transactions

    detected on the Up Hose (for example, a parity error or sequence error), or if the TLSB bus Read-Modify-Write operation is unsuccessful, the I/O port logs the error and generates an error interrupt to the CPU(s). 6.3.7 Extended NVRAM Write Transactions The Memory Channel write transaction is used to deliver a block of data, along with its TLSB physical address, to the remote I/O bus.

  • Page 146: Addressing

    When an I/O port receives a window write status return packet on the Up Hose, it decrements its remote adapter node buffer counters and discards the packet. If the Memory Channel write address range does not fall within the range of an associated valid outgoing Down Hose Range register, the I/O port dis- cards the transaction and sets ICCNSE<3>...

  • Page 147: Accessing Remote I/O Node Csrs Through Direct I/O Window Space

    must not overwrite a mailbox that is still in use (<DONE> not set by the I/O port). The I/O system architecture requires that there be only a single software- visible mailbox pointer CSR (TLMBPR) address. Once the software has built a mailbox structure in main memory, it loads the I/O port’s TLMBPR register with the double hexword aligned address of the mailbox.

  • Page 148: Sparse Address Space Reads

    Figure 6-3 Sparse Address Space Reads TLSB_BANK_NUM TLSB_ADR<39:0> <3:0> Byte-Aligned I/O Address <4:3> Byte Length Field <31:5> Byte-Aligned I/O Address <26:0> <33:32> Space Select Field 01 = Sparse memory space 10 = Sparse I/O space 11 = Sparse configuration space <35:34>...

  • Page 149: Sparse Address Space Writes

    Table 6-3 Sparse Address Space Read Field Descriptions Field Description TLSB_BANK_NUM<3:0> Contains the TLSB commander virtual ID (VID). Indicates the address is an I/O address space reference. It will al- TLSB_ADR<39> ways be a one if the reference is in I/O address space. Defines the responder TLSB node as follows: TLSB_ADR<38:36>...

  • Page 150: Sparse Address Space Writes

    Figure 6-5 Sparse Address Space Writes TLSB_BANK_NUM TLSB_ADR<39:0> <3:0> Byte-Aligned I/O Address <31:5> Byte-Aligned I/O Address <26:0> <33:32> Space Select Field 01 = Sparse memory space 10 = Sparse I/O space 11 = Sparse configuration space <35:34> Hose number in port being addressed (0 - 3) <38:36>...

  • Page 151: Sparse Address Space Write Field Descriptions

    Table 6-4 Sparse Address Space Write Field Descriptions Field Description TLSB_BANK_NUM<3:0> Contains the TLSB commander virtual ID (VID). Indicates the address is an I/O address space reference. It will al- TLSB_ADR<39> ways be one if the reference is in I/O address space. Defines the responder TLSB node as follows: TLSB_ADR<38:36>...

  • Page 152: Dense Address Space Transactions

    Table 6-5 Sparse Address Write Length Encoding Valid Bits Length <6,4,2,0> <1:0> TLSB Quadword Transmit on Hose 0001 63–0 (QW 0) 127–64 (QW 1) 001X 191–128 (QW 2) 01XX 192–255 (QW 3) 1XXX NOTE: The byte-length code is transmitted on the hose as LEN<1:0>. The Length field is equivalent to TLSB_ADR<4:3>...

  • Page 153: Dense Address Space Transaction Field Descriptions

    Table 6-6 Dense Address Space Transaction Field Descriptions Field Description TLSB_BANK_NUM<<3:0> Contains the TLSB commander virtual ID (VID). Indicates the address is an I/O address space reference. It will TLSB_ADR<39> always be one if the reference is in I/O address space. Defines the responder TLSB node as follows: TLSB_ADR<38:36>...

  • Page 154: Dense Address Space Write Data

    Figure 6-8 Dense Address Space Write Data LW 7 LW 6 LW 5 LW 4 LW 3 LW 2 LW 1 LW 0 TLSB_D<0> TLSB_D<32> TLSB_D<64> TLSB_D<96> TLSB_D<128> TLSB_D<160> TLSB_D<192> TLSB_D<224> BXB0821.AI The returned hexword data for a dense window read command is asserted on the first data word of the CSR write to broadcast space.

  • Page 155: Tlsb Interface

    6.5 TLSB Interface All TLSB bus transactions consist of one command/address cycle on the ad- dress bus and two data cycles on the data bus. The TLSB bus implements separate address and data buses to reduce memory latency, to allow the TLSB to adapt to different speed memories, and a range of bus cycle times (10 to 30 ns).

  • Page 156: Dma Transactions

    Table 6-7 Transaction Types Supported by the I/O Port TLSB_CMD<2:0> Initiates Responds to Command No-op Victim Read Write Read Bank Lock Write Bank Unlock CSR Read CSR Write 1 If the I/O port is in debug mode, it can initiate CSR reads and writes. 2 The I/O port initiates Write Broadcast CSR transactions only (unless in debug mode).

  • Page 157: Wrapped Reads

    Table 6-8 Wrapped Reads Byte Address Transaction Length <5:0-> Wrapped Octaword 0XXXXX 1XXXXX Octaword 0XXXXX Hexword 1XXXXX Hexword XXXXXX Double hexword 1 X = Don’t care. Interlocked Read/Unlock Write Transactions VAX CI-port architecture (VAXport) devices require Interlocked Read (IREAD) and Unlock Write (UWMask) transactions to access shared soft- ware data structures.

  • Page 158: Interrupt Transactions

    Modify-Write on the TLSB. The quadword of data that the I/O device sends in the masked write command contains the original data with the correct state of the lock bit, that is, bit <0> is clear. NOTE: There is no support for interlocked commands on the Futurebus+. DMA Unmasked Write Transactions The I/O port supports unmasked double hexword writes to memory.

  • Page 159: Write Csr (Interrupt) Data Format

    and so on. Figure 6-10 shows the format of the data used by the I/O port in the CSR write (interrupt) transaction. Figure 6-10 Write CSR (Interrupt) Data Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD CPU Mask <17:14>...

  • Page 160: Csr Transactions

    hose). The I/O port, however, could post up to five interrupts to the CPUs at IPL 17 (one per hose plus one I/O port generated error interrupt). When a CPU reads a specific TLILIDx register that contains a valid vector, the I/O port builds an interrupt status return packet and returns it on the appropriate Down Hose to the I/O adapter module.
  • Page 161 in strict first-come, first-served order. Any other writes to the TLMBPR register by a CPU that already has two mailbox transactions pending is NO ACKed. A further constraint is that only one mailbox transaction can be processed by the I/O port at any time. All further mailbox transactions in the TLMBPR queue are put on hold until the previous mailbox transac- tion completes.

  • Page 162: Tlsb Arbitration

    If the Error bit is set in the window Read Data Return packet, the I/O port generates a TLSB CSR (broadcast) write to the CSR Read Data Return Er- ror Register in CSR broadcast space. Data written is Unpredictable. The flow is the same as in the normal case.

  • Page 163: Node 8 I/O Port Arbitration Mode Selection

    6.5.2.1 Node 8 I/O Port Arbitration Mode Selection Several mode-selectable lockout avoidance algorithms are implemented to guarantee that the node 8 I/O port will eventually allow other nodes to ac- cess a given memory bank on the TLSB while allowing software to fine- tune I/O performance.

  • Page 164: Minimum Latency Mode

    Figure 6-11 Minimum Latency Mode RESET REQ8_HIGH Notes: WIN = (GRANT* - NOP) ELSE WIN or LOSE LOSE = (REQ8_LOW * PREQ<n>*-WIN) or PREQ<n> PREQ<n>(potential request) = REQ8_LOW (-ARB_SUPPRESS* -BANK_AVL<n>* ELSE -REQ8_HIGH* -ARB_CYCLE) BXB0811.AI Note that NEXT_REQ_HI<n> would have become asserted in cycle 6 even if the I/O port did not request the bus in cycles 3–6.

  • Page 165: Read-Modify-Write

    the Write Bank Unlock portion of a Read-Modify-Write operation. Figure 6-13 shows the flow for this arbitration mode. Figure 6-13 Toggle 50% High/50% Low Mode RESET Notes: WIN = (GRANT* - NOP) REQ8_HIGH LOSE = (REQ8_LOW * PREQ<n>*-WIN) ELSE WIN or LOSE PREQ<n>(potential request) = (-ARB_SUPPRESS* -BANK_AVL<n>*...

  • Page 166: Bank Collision Effect On Priority

    commands are necessary to ensure an atomic operation and maintain cache coherency. 6.5.2.3 Bank Collision Effect on Priority A bank collision occurs when two commanders request the same bank, the first one wins, the second one gets the bus 2 cycles later and finds that it is not allowed to access that bank.

  • Page 167: Hose Interface

    6.6 Hose Interface The I/O port communicates with the I/O bus adapters over dual-cable buses. These buses are called hoses. The I/O subsystem architecture sup- ports four separate I/O bus adapters, as shown in Figure 6-1. Each hose consists of two separate unidirectional interconnects: a Down Hose, which transmits command/address and data from the I/O port to the I/O bus adapter module;...

  • Page 168: Window Space Mapping

    port receives a Window Status Return packet on the Up Hose, it decre- ments that hose’s counter. The I/O port does not transmit window read/write command packets on the Down Hose when that hose’s counter equals zero. Thus, the I/O adapter’s Down Hose window FIFO never over- flows.

  • Page 169: Sparse Address Mapping

    6.6.2.1 Sparse Address Mapping A sparse address space uses low-order TLSB address bits to encode the size of the access and its byte offset. The I/O port interprets an Alpha physical address in the window space as: • PA<xx:5> - byte-aligned remote I/O bus address •...

  • Page 170: Down Hose Signals

    Table 6-10 Down Hose Signals Signal Description Down Data Lines. Asserted by the I/O port. Carry command/address, DND<31:0> L data, or transaction status information. Down Parity. Carry odd parity across DND<31:0>. DNP L DNDATAVAL L Down Data Valid. This line is asserted by the I/O port for each valid cycle of a Down Hose packet.

  • Page 171: Hose Packet Specifications

    Table 6-12 UPCTL<3:0> Encoding UPCTL<3:0> Meaning First Hose Cycle of a Packet Packet Type DMA Read 0001 IREAD 0010 Mailbox Status Return 0100 0101 DMA Unmasked Write W/Data DMA Masked Write W/Data 0111 INTR/IDENT 1000 Window Write Status 1100 Dense Window Read Return 1101 Sparse Window Read Return 1110...

  • Page 172: Hose Status Signals

    Table 6-13 Hose Status Signals Signals Meaning I/O port interrupts the CPU(s) on the indicated transitions, if interrupts are enabled PWROK H ERROR L CBLOK L L -> H I/O adapter just finished powering up - Adapter ready to receive and process packets. I/O port generates in- terrupt to CPU(s) on transition of PWROK.

  • Page 173: Mailbox Command Packet

    Mailbox Command Packet The Mailbox Command packet is used by processors to access control and status registers in adapters on the XMI and Futurebus+. Status for the Mailbox Command packet is returned in a separate packet on the Up Hose called a Mailbox Status Return packet. Only one Mailbox Command packet can be issued at a time by the I/O port, regardless of the Down Hose for which it is destined.

  • Page 174: Dma Read Data Return Packet

    Table 6-15 Mailbox Command Packet Description Field Description Command <31:14> is specific to the remote bus (for example, XMI or Clock 1, <31:14> Futurebus+) rather than the I/O port, and contains the remote bus opera- tion. It can include fields such as read/write, address only, address width, data width, and so on.

  • Page 175: Dma Read Data Return Packet Description

    The DMA Read Data Return packet is supported by the Mailbox Only, I/O Window, Full, and Memory Channel variants of the hose protocol. Table 6-16 gives the description of the DMA Read Data Return packet. Table 6-16 DMA Read Data Return Packet Description Field Description Tag <7:0>...

  • Page 176: Dma Read Data Return Packet With Error

    DMA Read Data Return packet with the error bit set is returned across the Down Hose. Figure 6-16 DMA Read Data Return Packet with Error DND <31:0> Clock cycle 24 23 22 13 12 11 10 TAG <7:0> E 0 0 0 0 0 0 0 0 0 0 1 0 LEN 0 0 0 0 0 0 0 0 BXB-0642-93 Table 6-17 gives the description of the DMA Read Data Return packet with...

  • Page 177: Intr/Ident Status Return Packet

    not return an INTR/IDENT Status Return packet. Figure 6-17 shows the INTR/IDENT Status Return packet. Figure 6-17 INTR/IDENT Status Return Packet DND <31:0> Clock cycle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BXB-0643-93...

  • Page 178: Sparse Window Read Command Packet Description

    Table 6-19 Sparse Window Read Command Packet Description Field Description Are always zero. Clock 1, <31:30> Virtual ID of the TLSB commanding node. The VID indicates which CPU Clock 1, <29:26> is requesting the data. The VID is returned on the Up Hose in all window return data/status packets so that the I/O port can target the requesting commanding node with the data or status of the transaction.

  • Page 179: Sparse Window Write Command Packet

    Figure 6-19 Sparse Window Write Command Packet Clock cycle DND <31:0> 31 30 29 26 25 15 14 13 12 11 Zero Zero Byte Aligned Address <31:0> Data Longword 0 Data Longword 1 BXB-0570-94 Table 6-20 gives the description of the Sparse Window Write Command packet.

  • Page 180: Dense Window Read Command Packet

    Table 6-20 Sparse Window Write Command Packet Description Field Description Are always zero. Clock 1, <31:30> Virtual ID of the TLSB commanding node. The VID indicates which CPU Clock 1, <29:26> is requesting the data. The VID indicates which CPU is requesting the data.

  • Page 181: Dense Window Read Command Packet Description

    Table 6-21 Dense Window Read Command Packet Description Field Description Are always zero. Clock 1, <31:30> Virtual ID of the TLSB commanding node. The VID indicates which CPU Clock 1, <29:26> is requesting the data. The VID is returned on the Up Hose in all window return data/status packets so that the I/O port can target the requesting commanding node with the data or status of the transaction.

  • Page 182: Dense Window Write Command Packet

    Figure 6-21 Dense Window Write Command Packet Clock cycle DND <31:0> 31 30 29 26 25 15 14 13 12 11 Zero Zero Byte Aligned Address <31:0> Byte Mask Bits <31:0> Data Longword 0 Data Longword 1 Data Longword 2 Data Longword 3 Data Longword 4 Data Longword 5...

  • Page 183: Byte Mask Field

    Table 6-22 Dense Window Write Command Packet Description Field Description Are always zero. Clock 1, <31:30> Virtual ID of the TLSB commanding node. The VID indicates which CPU Clock 1, <29:26> is requesting the data. The VID is returned on the Up Hose in all window return data/status packets so that the I/O port can target the requesting commanding node with the data or status of the transaction.

  • Page 184: Up Hose Packet Specifications

    Figure 6-23 Memory Channel Write Packet Clock cycle DND <31:0> 31 30 29 15 14 13 12 11 10 11110 Zero ADR<39:32> Byte Aligned Address <31:0> Data Longword 0 Data Longword 1 Data Longword 2 Data Longword 3 Data Longword 4 Data Longword 13 Data Longword 14 Data Longword 15...

  • Page 185: Mailbox Status Return Packet

    Table 6-23 Memory Channel Write Packet Description Field Description Always zero. Clock 1, <31> Error. Always sent as zero by the I/O port. Clock 1, <30> Are always zero. Clock 1, <29:16> Command field. It is always set to a code of 11110 by the I/O port to indi- Clock 1, <15:11>...

  • Page 186: Dma Read Packet

    Table 6-24 Mailbox Status Return Packet Description Field Description The return data longword 0 and 1 fields, respectively. The return data Clock 1 and 2, fields contain read data in response to Mailbox Command packets that <31:0> were reads. This data is Unpredictable when responding to Mailbox Com- mand packets that were writes.

  • Page 187: Dma Read Packet Description

    Table 6-25 DMA Read Packet Description Field Description The TAG<7:0> field allows the subsequent DMA Read Data Return packet Clock 1, <31:24> on the Down Hose to be associated with a DMA Read Data packet on the Up Hose. The tag is generated by the I/O bus adapter. Are always zero.

  • Page 188: Interlock Read Packet

    Figure 6-26 Interlock Read Packet UPD <31:0> UPCTL 24 23 11 10 0 0 1 0 TAG<7:0> ADR <39:32> ADR <31:0> x x x x * = hose cycle BXB-0640-93 Table 6-27 gives the description of the IREAD packet. Table 6-27 Interlock Read Packet Description Field Description Clock 1, <31:24>...

  • Page 189: Dma Masked Write Packet

    DMA Masked Write with Data The DMA Masked Write Packet is a request on the Up Hose from the I/O bus adapter to the I/O port for a TLSB data write transaction. Any combination of mask bits is allowed. However, the I/O bus adapter may or may not support this capability.

  • Page 190: Dma Masked Write Packet Description

    Table 6-29 DMA Masked Write Packet Description Field Description Don’t Care. These bits, which normally form the TAG field, are don’t Clock 1, <31:24> care, since DMA Masked Write packets are disconnected and have no corresponding return packet. Are always zero. Clock 1, <23:11>...

  • Page 191: Dma Unmasked Write Packet

    DMA Unmasked Write with Data The DMA Unmasked Write packet is a request on the Up Hose from the I/O bus adapter to the I/O port for a TLSB data write transaction. The data length of the unmasked write is always a double hexword and the LEN code must indicate a double hexword (100).

  • Page 192: Intr/Ident Status Return Packet

    Table 6-31 DMA Unmasked Write Packet Description Field Description Don’t Care. These bits, which normally form the TAG field, are don’t Clock 1, <31:24> care, since DMA Unmasked Write packets are disconnected and have no corresponding return packet. Are always zero. Clock 1, <23:11>...

  • Page 193: Sparse Window Read Data Return Packet

    Table 6-32 INTR/IDENT Status Return Packet Description Field Description Don’t Care. These bits, which normally form the TAG field, are don’t care, Clock 1, <31:24> since only one interrupt per IPL can be pending at a time and the corre- sponding INTR/IDENT Status Return packet can be easily identified by the IPL field.

  • Page 194: Sparse Window Read Data Return Packet Description

    Table 6-33 Sparse Window Read Data Return Packet Description Field Description Is always zero. Clock 1, <31> Error. Set by the remote I/O bus adapter if any errors were detected on Clock 1, <30> the transfer. Virtual ID of the TLSB commander node. This enables the I/O port to as- Clock 1, <29:26>...

  • Page 195: Dense Window Read Data Return Packet

    Figure 6-31 Dense Window Read Data Return Packet UPD <31:0> UPCTL 31 30 29 28 27 26 25 1 1 0 1 Zero Count Zero x x x x Data Longword 0 Data Longword 1 x x x x Data Longword 2 x x x x Data Longword 3 x x x x...

  • Page 196: Window Write Status Return Packet

    Window Write Status Return Packet The Window Write Status Return packet is used by adapters on remote buses that support I/O window space packets to return the completion status of a previously issued dense/sparse window write command packet. The command field value of the Window Write Status Return packet is C (hex).

  • Page 197: Hose Errors

    6.6.5 Hose Errors Four types of errors affect the hoses: • Parity errors on the transmitted data/control information • Illegal packet errors • FIFO overflow errors • I/O port internal errors Parity errors are detected on all Up Hoses and have corresponding CSR er- ror bits to indicate the failure to the system.

  • Page 198: I/O Port Error Handling

    6.7 I/O Port Error Handling The I/O port provides a high reliability electrical environment. Conse- quently, error handling is biased toward detection rather than correction. The I/O port attempts to retain state for system software to determine the severity level and recoverability of any error. However, due to the deep pipelined nature of the protocol, the amount of state saved is limited.

  • Page 199: Error Reporting

    If the I/O port detects a hard internal error. it sets the appropriate error bit in either the ICCNSE register or one of the IDPNSEn registers, which- ever is applicable. The I/O port then posts an IPL 17 error interrupt to the processor(s) to inform the operating system of the error if interrupts are enabled (ICCNSE<INTR_NSES>...

  • Page 200: Tlsb_Fault

    Each IDR on the I/O port receives 64 data bits and 8 ECC bits from the TLSB. Error checking is performed and if a data error is detected, the IDR(s) set the appropriate error bit in the TLESRn register. The IDR(s) also informs the ICR that a data error, either hard or soft, has been de- tected.

  • Page 201: Ipl 17 Error Interrupts

    another node and ensure that TLSB_FAULT is only asserted for two cy- cles. When the I/O port detects assertion of TLSB_FAULT on the TLSB, it im- mediately aborts all outstanding transactions and resets to a known state. The I/O port deasserts its REQUEST signal no later than two cycles from the assertion of TLSB_FAULT.

  • Page 202: Address Bus Errors

    Hose PWROK Transitioned and Hose Error are technically hose errors, not internal I/O port errors. However, they are handled by the I/O port in the same manner as internal errors. The posting of IPL 17 error interrupts are enabled by software by setting ICCNSE<INTR_NSES>...

  • Page 203: Address Bus Parity Errors

    The I/O port assertion checks TLSB_CMD_ACK only when it is being as- serted by the the I/O port. If the I/O port detects a mismatch, it sets <ACKTCE> and asserts TLSB_FAULT. The I/O port assertion checks TLSB_ARB_SUP only when it is being as- serted by the I/O port.

  • Page 204: Data Bus Errors

    tected, the I/O port does not issue the transaction on the TLSB. It simply aborts that transaction by transmitting a UTV_ERROR_A (or B) code across its internal TL_CMD bus to each IDR. The I/O port then posts an IPL 17 interrupt on the TLSB, if enabled by ICCNSE<INTR_NSES>. 6.7.8 Data Bus Errors Data bus errors are either ECC-detected errors on data transfers or control errors on the data bus.

  • Page 205: Illegal Sequence Errors

    ting <UECC>. A UECC error causes the I/O port to set TLBER<UDE> and assert TLSB_DATA_ERROR. An IPL 17 is also posted, if enabled by software. If the error was detected on data that the I/O port was writing to memory, then TLESR<TDE>...

  • Page 206: Transmit Check Errors

    6.7.8.6 Transmit Check Errors The I/O port level checks the TLSB_D<255:0> and TLSB_ECC<31:0> fields when it is driving data on the TLSB bus. The I/O port sets <TCE> in its TLESRn register if it detects a mismatch. Since ECC is checked on the data received from the bus, a TCE error usually causes the I/O port to set one of <UECC>, <CWECC>, or <CRECC>.

  • Page 207: Hard I/O Port Errors

    • The TLFADRn registers record the address, command, and bank num- ber from the command. These registers can only hold information relative to one error. It is the responsibility of software to read and clear all error bits and status. Even when errors occur infrequently, there is a chance that a second error can occur before software clears all status from a previous error.

  • Page 208: Down Turbo Vortex Errors

    The ICR up Turbo Vortex interface checks for the following types of errors: • Parity errors • Sequence errors • Buffer overflow errors • Illegal command errors Reporting of up Turbo Vortex detected errors can be enabled by setting ICCNSE<INTR_NSES>, which results in the I/O port posting an IPL 17 interrupt.

  • Page 209: Miscellaneous I/O Port Errors

    assertion of this signal causes ICCNSE<DN_VRTX_ERRORn> to set. An IPL 17 interrupt will also be posted if ICCNSE<INTR_NSES> is set. When the down HDR completes processing of the failing packet, it at- tempts to assert DECR_PKT<n> to the ICR gate array. DECR_PKT<n> is only asserted if a packet was sent down the hose (for example, DMA read return with error packet).

  • Page 210: Hose Status Change Errors

    serts TLSB_FAULT. The catastrophic failure requires a reset of the I/O port to return the I/O port to a known state. 6.7.11.4 Hose Status Change Errors The IDPNSEn registers contain status information relating to the ability of the I/O adapter to receive commands and data from the Down Hose. These bits are <HOSEn_ERROR>...

  • Page 211: Kftia Block Diagram

    • One external hose connection • Optional multimode FDDI daughter card or UTP FDDI daughter card • Optional 4-Mbyte NVRAM daughter card • Onboard 128-Kbyte map RAM The integrated I/O port is comprised of two sections, as shown in Figure 6-34.

  • Page 212: Integrated I/O Section

    I/O port is a subset of what is implemented on the DWLPA. • Ethernet Controller 21040 (TULIP) Engineering Specification: De- scribes the Ethernet chip. Consult also the DEC 21040 Typical Motherboard Implementation. • ISP 1020 Intelligent SCSI Processor Technical Manual •...

  • Page 213: Pci Interface

    Figure 6-35 Integrated I/O Section of the KFTIA PCI 1 Down Hose 10BaseT HPC 1 Interface Ethernet 1 DC287 QLogic SCSI 3 ISP 1020 QLogic SCSI 2 ISP 1020 NVRAM Card PCI 1 PCI 0 Multimode FDDI FDDI or UTP Card HPC 0 10BaseT...

  • Page 214: Scsi Ports

    The PCI interface consists of the following sections: • Two HPC (hose to PCI) gate arrays • Map RAM • Up Hose control logic These sections are discussed below. HPC Gate Arrays Each HPC provides the connection between the internal hose and each PCI bus (PCI0 and PCI1).

  • Page 215: Ethernet Ports

    6.8.1.3 Ethernet Ports The integrated I/O port supports two Ethernet ports and uses the twisted- pair (10baseT) connection. The Ethernet port can sustain reception of back-to-back packets at full line speed with a 9.6 µs IPG (interpacket gap), or to transmit such back-to-back packets, due to its on-chip dual 256-byte FIFOs.

  • Page 216: Mailbox Transaction

    6.8.2.2 Mailbox Transaction All mailbox transactions are executed by the HPC as a PCI master. Mailbox transactions forwarded from the HDR can access a PCI I/O device through the PCI bus, an HPC CSR, or the map RAM. Mailbox transac- tions to PCI memory or I/O space on the PCI bus are sent to both PCI buses.

  • Page 217: Pci 0 And Pci 1 Interrupt Priority

    rupt’s vector and merging it with a programmable device IPL. The INTR/IDENT is then sent to the HDR over the Up Hose. Because the interrupt request lines of the devices are connected to more than one of the HPC’s 16 interrupt request input pins, software controls the interrupt priority of the devices on each PCI bus.

  • Page 219: Chapter 7 System Registers

    Chapter 7 System Registers The system registers are divided into two main groups: • TLSB registers • Node-specific registers TLSB registers are used for internode communications and transactions over the TLSB bus. Node-specific registers implement functions related to the operation of the module. Each node implements some TLSB required registers as well as node- specific registers.

  • Page 220: Register Address Mapping

    • When the value of a bit position is given explicitly in a register dia- gram, the information conveyed is as follows: Bit Value Designation Meaning Reads as zero; ignored on writes. Reads as one; ignored on writes. Does not exist in hardware. The value of the bit is Unpredictable on reads and ignored on writes.

  • Page 221: Tlsb Node Space Base Addresses

    Table 7-1 TLSB Node Space Base Addresses Physical Base Address (BB) Address Field <39:0> Node Module 34-Bit Range CPU, Memory FF 8800 0000 CPU, Memory FF 8840 0000 CPU, Memory FF 8880 0000 CPU, Memory FF 88C0 0000 ‘ CPU, Memory, I/O FF 8900 0000 CPU, Memory, I/O FF 8940 0000...

  • Page 222: Tlsb Registers

    7.3 TLSB Registers Table 7-2 lists the TLSB registers. Descriptions of registers follow. Table 7-2 TLSB Registers Modules That Mnemonic Name Address Implement Device Register BB+0000 CPU, Mem, I/O TLDEV Bus Error Register BB+0040 CPU, Mem, I/O TLBER TLCNR Configuration Register BB+0080 CPU, Mem, I/O Virtual ID Register...

  • Page 223: Tldev-Device Register

    TLDEV—Device Register Address BB + 0000 Access The TLDEV register is loaded during initialization with informa- tion that identifies a node. A zero value indicates an uninitialized node. 24 23 16 15 HWREV SWREV DTYPE BXB-0491-93 Table 7-3 TLDEV Register Bit Definitions Name Bit(s) Type...
  • Page 224 Table 7-3 TLDEV Register Bit Definitions (Continued) Name Bit(s) Type Function <15:0> R/W, 0 Device Type. Identifies the type of node as fol- DTYPE lows: bit <15> specifies a CPU node; bit <14> specifies a memory node; bit <13> specifies an I/O node.

  • Page 225: Tlber-Bus Error Register

    TLBER—Bus Error Register Address BB + 0040 Access The TLBER register contains bits that are set when a TLSB node detects errors in the TLSB system. The entire register is locked when the first error bit gets set in this register if TLCNR<LOFE> is set.

  • Page 226: Tlber Register Bit Definitions

    Table 7-4 TLBER Register Bit Definitions Name Bit(s) Type Function <31> W1C, 0 Data Timeout. Set when a commanding node times out waiting for a slave to assert TLSB_SEND_DATA. This is a system fatal er- ror that asserts TLSB_FAULT. This error is dis- abled if TLCNR<DTOD>...
  • Page 227 Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function <23> R, U Data Syndrome 3. A status bit set when the TLESR3 register contains status relative to the current data error. This bit is undefined when CRDE, CWDE, and UDE are zero. It is over- written on a second error of higher significance.
  • Page 228 Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function <16> W1C, 0 Uncorrectable Data Error. Set when <UECC> is set in any TLESRn register. This is a hard error that asserts TLSB_DATA_ ERROR. CPU: Set when <UECC> is set in any TLESRn register.
  • Page 229 Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function <6> W1C, 0 Acknowledge Transmit Check Error. Set ACKTCE when a transmit check error is detected on the TLSB_CMD_ACK signal. This is a system fatal error that asserts TLSB_FAULT. I/O: Also sets <NAE>...
  • Page 230 Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function <2> W1C, 0 Bank Available Violation Error. Set when a memory bank is addressed by a memory access command while the memory bank is busy. Also set when any node detects a CSR access com- mand while a CSR command is already in pro- gress.
  • Page 231 Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function <0> W1C, 0 Address Transmit Check Error. ATCE CPU: Set when a transmit check error is de- tected on the TLSB_ADR<39:3>, TLSB_ADR_PAR, TLSB_BANK_NUM<3:0>, TLSB_CMD<2:0>, or TLSB_CMD_PAR signals. This is a system fatal error that asserts TLSB_FAULT.

  • Page 232: Tlcnr-Configuration Register

    TLCNR—Configuration Register Address BB + 0080 Access The TLCNR register contains the TLSB system configuration setup and status information. Node-specific configuration information exists in node-specific registers. 31 30 29 28 27 22 21 20 19 14 13 12 11 RSVD RSVD VCNT NODE_ID HALT_A...

  • Page 233: Tlcnr Register Bit Definitions

    Table 7-5 TLCNR Register Bit Definitions Name Bit(s) Type Function <31> R/W, 0 Lock on First Error. If set, the node locks the LOFE TLBER and TLFADR registers when the first er- ror bit is set in the TLBER register. NRST <30>...
  • Page 234 Table 7-5 TLCNR Register Bit Definitions (Continued) Name Bit(s) Type Function <13> R/W, 1 Self-Test Fail B. When set, indicates that unit STF_B has not yet passed self-test. CPU: When set, indicates that CPU1 has not yet passed self-test. Initialized to zero for uniproces- sor module.
  • Page 235 Table 7-5 TLCNR Register Bit Definitions (Continued) Name Bit(s) Type Function <11:8> R/W, 0 Virtual Unit Count. This field indicates the VCNT number of virtual units contained in this mod- ule. CPU: Self-test firmware loads this field with a value of 1 on all uniprocessor modules and 2 on all dual-processor modules.
  • Page 236 Table 7-5 TLCNR Register Bit Definitions (Continued) Name Bit(s) Type Function <1> R/W, 0 Correctable Read Data Error Interrupt Dis- CRDD able. When set, TLSB_DATA_ERROR is not asserted on detection of a single-bit data error during a read command. Setting CRDD in all nodes disables correctable read data error inter- rupts.

  • Page 237: Tlvid-Virtual Id Register

    TLVID—Virtual ID Register Address BB + 00C0 Access The TLVID register contains the TLSB virtual identifiers assigned to a physical node. The virtual units can be CPUs or memory banks. The number of these units is presented in TLCNR<VCNT>. The units are addressed using virtual IDs that are assigned by writing the TLVID register.

  • Page 238: Tlvid Register Bit Definitions

    Table 7-6 TLVID Register Bit Definitions Name Bit(s) Type Function <31:8> R/W, 0 Reserved. Must be written as zero. RSVD <7:4> R/W, 0 Virtual ID B. Contains the virtual ID for unit VID_B B in this node. Reads zero if unimplemented. CPU: Contains the virtual ID for CPU1.

  • Page 239: Tlmmrn-Memory Mapping Registers

    TLMMRn—Memory Mapping Registers Address BB + 0200 to BB + 03C0 Access W (CPU), R/W (I/O) The TLMMRn registers contain the mapping information for per- forming bank decode. RSVD INTLV ADRMSK ADDRESS VALID SBANK RSVD INTMASK BXB-0757-93 Table 7-7 TLMMRn Register Bit Definitions Name Bit(s) Type...

  • Page 240: Interleave Field Values For Two-Bank Memory Modules

    Table 7-7 TLMMRn Register Bit Definitions (Continued) Name Bit(s) Type Function <10:8> CPU, W, 0 Interleave. Lower address bits used in inter- INTLV I/O, R/W, 0 leaving. This field is compared to physical ad- dress lines TLSB_ADR<8:6>. Table 7-8 gives <INTLV>...

  • Page 241: Address Ranges Selected By Adrmask Field Values

    Table 7-9 Address Ranges Selected by ADRMASK Field Values Address TLSB_ADR Bits TLSB_ADR Bits <ADRMASK> Range Compared Masked 64 Mbytes <39:26> ---- 128 Mbytes <39:27> <26> 256 Mbytes <39:28> <27:26> 512 Mbytes <39:29> <28:26> 1 Gbyte <39:30> <29:26> 2 Gbytes <39:31>...

  • Page 242: Tlfadrn-Failing Address Registers

    TLFADRn—Failing Address Registers Address BB + 0600, 0640 Access The TLFADRn registers contain status information associated with an error condition. Some nodes may not preserve this information for all error types. Therefore, field valid bits are used to indicate which fields contain data. 13 12 11 10 9 8 23 22 21 20 19 18 17 16...
  • Page 243 Table 7-10 TLFADRn Register Bit Definitions (Continued) Name Bit(s) Type Function TLFADR1 <24> W1C, 0 Address Valid. Set when <FADR> contains a valid ADRV address from a bus transaction. <23:20> R, U Failing Bank Number. The bank number field FBANK from the command that resulted in an error.

  • Page 244: Tlesrn-Error Syndrome Registers

    TLESRn—Error Syndrome Registers Address BB + 0680 through 0740 Access The TLESRn registers contain the status information on a data er- ror within a 64-bit slice of the data. TLESR0 contains the error syndrome and status derived from TLSB_D<63:0>, TLSB_ECC<7:0>, and TLSB_DATA_VALID<0>. TLESR1 contains the error syndrome and status derived from TLSB_D<127:64>, TLSB_ECC<15:8>, and TLSB_DATA_VALID<1>.
  • Page 245 Table 7-11 TLESRn Register Bit Definitions (Continued) Name Bit(s) Type Function <23> RO, 0 CPU 1. When set together with <TDE>, indicates CPU1 that CPU1 was involved with sourcing the data er- ror. This bit is Unpredictable when <TDE> is clear and also when CRECC, CWECC, and UCE are zero.
  • Page 246 Table 7-11 TLESRn Register Bit Definitions (Continued) Name Bit(s) Type Function <16> W1C, 0 Transmitter During Error. A status bit set when data transmitted by a node results in error. This bit is Undefined when <CRECC>, <CWECC>, and <UECC> are zero. <15:8>...
  • Page 247 Four error bits in the TLBER register will set as a result of the five error bits in this register. • CRECC sets TLBER<CRDE> • CWECC sets TLBER<CWDE> • UECC sets TLBER<UDE> • TCE, when no ECC error detected, sets TLBER<FDTCE> •...

  • Page 248: Tlilidn-Interrupt Level Ident Registers

    TLILIDn—Interrupt Level IDENT Registers Address BB + 0A00 through 0AC0 Access Each of the four TLILIDn registers is the topmost (oldest) entry in a queue of the interrupts for that IPL. A read from this register sends the "oldest" interrupt IDENT to the CPU that requests it. When all active interrupts have been read, the TLILIDn register returns zeros.

  • Page 249: Tlcpumask-Cpu Interrupt Mask Register

    TLCPUMASK—CPU Interrupt Mask Register Address BB + 0B00 Access The TLCPUMASK register is used to determine which CPUs are to service interrupts. The contents of this register is combined with the interrupt level to form the data to be written to the TLI/OINTRn register.

  • Page 250: Tlmbpr-Mailbox Pointer Registers

    TLMBPR—Mailbox Pointer Registers Address BB + 0C00 Access The TLMBPR register posts mailbox requests in an I/O port for ac- cess to a CSR on an external I/O bus. Software access to this regis- ter is through the single address BB+0C00. CPU hardware selects one of the 16 registers by asserting the value of the CPU’s virtual ID on TLSB_BANK_NUM<3:0>.

  • Page 251: Mailbox Data Structure Description

    Figure 7-1 Mailbox Data Structure 48 47 40 39 32 31 QW 0 MASK HOSE QW 1 RBADR <63:0> QW 2 WDATA <63:0> UNPREDICTABLE QW 3 RDATA <63:0> QW 4 STATUS QW 5 UNPREDICTABLE QW 6 UNPREDICTABLE QW 7 BXB-0174 C-94 Table 7-15 gives the description of the mailbox data structure fields.
  • Page 252 Table 7-15 Mailbox Data Structure Description (Continued) Bit(s) Name Description <63:0> RDATA Read Data. For read commands, contains the data returned. For write data commands, the field is Unpredictable. <0> Done. For read commands, indicates that the <ERR>, <STATUS>, and <RDATA> fields are valid. For all commands, indicates that the mailbox structure may be safely modified by host software.

  • Page 253: Tlipintr-Interprocessor Interrupt Register

    TLIPINTR—Interprocessor Interrupt Register Address BSB + 0040 Access The TLIPINTR register is used by CPU nodes to signal inter- processor interrupts. 16 15 RSVD MASK BXB-0497-93 Table 7-16 TLIPINTR Register Bit Definitions Name Bit(s) Type Function <31:16> W, 0 Reserved. Must be zero. RSVD MASK <15:0>...

  • Page 254: Tliointrn-I/O Interrupt Registers

    TLIOINTRn—I/O Interrupt Registers Address BSB + 0100 through 0200 Access The TLIOINTRn registers are used by the I/O nodes to signal inter- rupts from the TLSB I/O system to processors. 20 19 18 17 16 15 RSVD VID_MASK IPL 14 INTR IPL 15 INTR IPL 16 INTR IPL 17 INTR...
  • Page 255 means that all CPUs accept writes to these registers. Multiple writes to a register post multiple interrupts. Reads to these locations produce Unpre- dictable results. A CPU receiving one of the four bits set in its target assignment is ex- pected to respond by reading a TLILIDn register in the I/O node and dis- patch an interrupt based on the IDENT vector.

  • Page 256: Tlwsdqr4-8-Window Space Decr Queue Counter Registers

    TLWSDQR4-8—Window Space Decr Queue Counter Registers Address BSB + 0400 through 0500 Access The TLWSDQRn registers are used by an I/O node to inform CPU nodes when a window space address register becomes available. One register is assigned to each I/O node by physical node ID (for example, TLWSDQR5 to node 5).

  • Page 257: Tlrmdqrx-Memory Channel Decr Queue Counter Register X

    TLRMDQRX—Memory Channel Decr Queue Counter Register X Address BSB + 0600 Access The TLRMDQR register X is used by an I/O node to inform all nodes when a Memory Channel address register becomes avail- able. One I/O port in physical nodes 4 through 7 that is enabled to handle Memory Channel transactions issues writes to this register.

  • Page 258: Tlrmdqr8-Memory Channel Decr Queue Counter Register 8

    TLRMDQR8—Memory Channel Decr Queue Counter Register 8 Address BSB + 0640 Access The TLRMDQR register 8 is used by an I/O node to inform all nodes when a Memory Channel address register becomes available. An I/O port in physical node 8 issues writes to this register. If the I/O node acknowledges the CSR write command, it must cycle the data bus and provide data with good ECC.

  • Page 259: Tlrdrd-Csr Read Data Return Data Register

    TLRDRD—CSR Read Data Return Data Register Address BSB + 0800 Access The TLRDRD register is used by I/O nodes to return data read from a remote CSR window space read command and complete the remote CSR read command. The CPU virtual ID is asserted on the TLSB_BANK_NUM<3:0>...

  • Page 260: Tlrdre-Csr Read Data Return Error Register

    TLRDRE—CSR Read Data Return Error Register Address BSB + 0840 Access The TLRDRE register is used by I/O nodes to signal an error dur- ing a remote CSR window space read command and complete the remote CSR read command. The data returned is Unpredictable. The CPU virtual ID is asserted on the TLSB_BANK_NUM<3:0>...

  • Page 261: Tlmcr-Memory Control Register

    TLMCR—Memory Control Register Address BSB + 1880 Access The TLMCR register is used by memory nodes to set DRAM timing rates. DRAM timing is dependent on bus cycle time and must be written into each memory node to ensure the most efficient mem- ory operation.

  • Page 262: Cpu Module Registers

    7.4 CPU Module Registers CPU module registers are divided into four groups: • Module-specific registers • CPU0-specific registers • CPU1-specific registers • Gbus registers The first three groups of registers are implemented in TLSB node space for visibility. Gbus registers reside in the node private space. NOTE: Accesses by a CPU to its own Gbus registers are treated as private accesses and are performed through the TLPRIVATE location in broadcast space (BSB + 0000).

  • Page 263: Cpu Module Registers

    Table 7-20 CPU Module Registers Mnemonic Name Address Module Registers Diagnostic Setup Register BB+1000 TLDIAG DTag Data Register BB+1040 TLDTAGDATA DTag Status Register BB+1080 TLDTAGSTAT TLMODCONFIG CPU Module Configuration Register BB+10C0 Console Communications Register 0 for CPU0 BB+1200 TLCON00 DIGA Communications Test Register 0 for DIGA1 BB+1240 TLCON0A DIGA Communications Test Register 0 for DIGA2...

  • Page 264: Gbus Registers

    Table 7-20 CPU Module Registers (Continued) Mnemonic Name Address Module Registers Memory Channel Range Register for channel 0 BB+1E00 RM_RANGE_0A Memory Channel Range Register for channel 0 BB+1E40 RM_RANGE_0B Memory Channel Range Register for channel 1 BB+1E80 RM_RANGE_1A RM_RANGE_1B Memory Channel Range Register for channel 1 BB+1EC0 CPU Chip Registers Interrupt Mask Register for CPU0...

  • Page 265: Tldiag-Diagnostic Setup Register

    TLDIAG—Diagnostic Setup Register Address BB + 1000 Access The TLDIAG register is used to configure the module for the vari- ous diagnostic modes required for a complete module-level self- test. Only one diagnostic setup register is specified, shared be- tween the two CPUs. 16 15 14 13 12 11 10 RSVD RSVD...
  • Page 266 Table 7-22 TLDIAG Register Bit Definitions (Continued) Name Bit(s) Type Function <13> R/W, 0 Assert Fault. When set, clearing <FRIGN> causes ASRT_FLT TLSB_FAULT to be asserted to the bus. On power-up re- set, this bit is clear, as TLSB_FAULT should not be as- serted.
  • Page 267 Table 7-22 TLDIAG Register Bit Definitions (Continued) Name Bit(s) Type Function <1> W, 0 DTag Write. When set, causes the DTag entry at the in- DTWR dex specified by the next memory space read to be writ- ten with the value in the TLDTAGDATA and TLDTAG- STAT registers.

  • Page 268: Tldtagdata-Dtag Data Register

    TLDTAGDATA—DTag Data Register Address BB + 1040 Access Diagnostics test the DTag RAMs by writing a value to the DTag and reading the value back to check that the two match. On diag- nostic DTag writes, the TLDTAGDATA register is used to set up the DTag data to be written.

  • Page 269: Tldtagstat-Dtag Status Register

    TLDTAGSTAT—DTag Status Register Address BB + 1080 Access Diagnostics test the DTag status RAMs by writing a value to <DT_STAT> and reading the value back to check that the two match. On diagnostic DTag writes, the TLDTAGSTAT register is used to set up the <DT_STAT> value to be written. On diagnostic DTag reads, the TLDTAGSTAT register is used to report the <DT_STAT>...

  • Page 270: Tlmodconfig-Cpu Module Configuration Register

    TLMODCONFIG—CPU Module Configuration Register Address BB + 10C0 Access The TLMODCONFIG register is set by console code to show the module configuration. 14 13 17 16 10 9 RSVD FAULT_DIS CPU_PIPE_DIS SYS_PIPE_DIS BQ_MAX_ENT CQ_MAX_ENT BCIDLETIM: BC Idle Time RM_SIZE LOCKOUT_EN BCACHE_SIZE CPU1_DIS CPU0_DIS...
  • Page 271 Table 7-25 TLMODCONFIG Register Bit Definitions (Continued) Name Bit(s) Type Function <15:13> R/W, 4 Bus Queue Maximum Entries. Indicates the maxi- BQ_MAX_ENT mum number of bus queue entries supported. Not all values are supported. <12:10> R/W, 4 Cache Queue Maximum Entries. Indicates the CQ_MAX_ENT maximum number of cache queue entries supported.

  • Page 272: Tlepaerr- Adg Error Register

    TLEPAERR— ADG Error Register Address BB + 1500 Access The ADG Error Register contains CPU module error bits. These bits are set as a result of errors detected in the ADG. 16 15 14 13 12 11 10 RSVD NO_ACK CSR_WR_NXM WSPC_RD_PEND <1:0>...

  • Page 273: Tlepaerr Register Bit Definitions

    Table 7-26 TLEPAERR Register Bit Definitions Name Bit(s) Type Function <31:18> R/W, 0 Reserved. Must be written as zeros. RSVD <17:16> W1C, 0 No Acknowledgment. No acknowledgment from NO_ACK one of the DECchip 21164 processors. Bit <16> ap- plies to CPU0; bit <17> to CPU1. <15>...
  • Page 274 Table 7-26 TLEPAERR Register Bit Definitions (Continued) Name Bit(s) Type Function <3> W1C, 0 MMG to ADG Address Parity Error #1. Set when M2AAPE1 the ADG detects a parity error on the address bus be- tween CPU1 MMG and the ADG. A parity check is performed after the ADG has assembled the CPU ad- dress and cmd/addr parity, as piped from the MMG, and combined it with the CPU command sent directly...

  • Page 275: Tlepderr-Diga Error Register

    TLEPDERR—DIGA Error Register Address BB + 1540 Access The TLEPDERR register contains CPU module error bits. These bits are set as a result of errors detected in the MMG or any of the DIGA chips. This register resides in DIGA0. RSVD GBTO: Gbus Timeout Error D2DCPE0: DIGA to DIGA CSR Parity Error #0...

  • Page 276: Tlepderr Register Bit Definitions

    Table 7-27 TLEPDERR Register Bit Definitions Name Bit(s) Type Function <31:3> R/W, 0 Reserved. Must be written as zeros. RSVD <2> W1C, 0 Gbus Timeout Error. Set when DIGA0 issues a GBTO Gbus read and fails to receive Gbus Acknowledge within the Gbus timeout period.

  • Page 277: Tlepmerr-Mmg Error Register

    TLEPMERR—MMG Error Register Address BB + 1580 Access The TLEPMERR register contains CPU module error bits. These bits are set as a result of errors detected in the MMG. This regis- ter also contains the node reset status bit. RSVD RSTSTAT D2DCPE3: DIGA to DIGA CSR Parity Error #3 D2DCPE2: DIGA to DIGA CSR Parity Error #2...

  • Page 278: Tlepmerr Register Bit Definitions

    Table 7-28 TLEPMERR Register Bit Definitions Name Bit(s) Type Function <31:7> R/W, 0 Reserved. Must be written as zeros. RSVD <6> W1C, 0 Node Reset Status. When set, indicates that the RSTSTAT node was reset by writing 1 to TLCNR<NRST>. <5>...
  • Page 279 Table 7-28 TLEPMERR Register Bit Definitions (Continued) Name Bit(s) Type Function <2> W1C, 0 DIGA to MMG CSR Parity Error. Set when the D2MCPE MMG detects a parity error on the DIGA to DIGA CSR bus. This error can occur when a CSR in the MMG is being written or read.

  • Page 280: Tlep_Vmg-Voltage Margining Register

    TLEP_VMG—Voltage Margining Register Address BB + 15C0 Access The TLEP_VMG register is implemented in DIGA1. It drives the voltage margining circuit on the CPU module to vary the 5 V and 3.3 V supplies. The otherwise unused (on DIGA1) interrupt lines are used for this function.

  • Page 281: Tlintrmask0-1-Interrupt Mask Registers

    TLINTRMASK0–1—Interrupt Mask Registers Address BB + 1100, BB + 1140 Access The TLINTRMASK0–1 registers are used to enable interrupts to the CPUs. TLINTRMASK0 controls interrupts on CPU0 and TLIN- TRMASK1 on CPU1. RSVD Ctrl/P HALT ENA HALT ENA INTIM_ENA IP_ENA IPL17_ENA IPL16_ENA IPL15_ENA...

  • Page 282: Tlepderr Register Bit Definitions

    Table 7-30 TLEPDERR Register Bit Definitions Name Bit(s) Type Function <31:9> R/W, 0 Reserved. Must be written as zeros. RSVD <8> R/W, 0 Ctrl/P Halt Enable. Enables halt through ^P if Ctrl/P_HALT_ENA <TLSB_SECURE> of GBUS$MISCR is not set, and if a ^P Halt interrupt is received from the Gbus.

  • Page 283: Tlintrsum0-1-Interrupt Source Registers

    TLINTRSUM0–1—Interrupt Source Registers Address BB + 1180, BB + 11C0 Access The DECchip 21164 has seven interrupt lines. They are as follows: 1. IRQ<3:0> - Interrupt request lines mapping to IPL17:IPL14 2. SYS_MCH_CHK_IRQ - Machine check interrupt request 3. MCH_HLT_IRQ - Machine halt interrupt request 4.

  • Page 284: Tlintrsum Register Bit Definitions

    Table 7-31 TLINTRSUM Register Bit Definitions Name Bit(s) Type Function <31:29> R/W, 0 Reserved. Must be written as zeros. RSVD <28> R, 0 Halt. CPU halt was written in TLCNR<HALT_x> HALT (this CPU) and TLINTR<HALT_ENA> is set. <27> W1C, 0 Ctrl/P Halt.
  • Page 285 Table 7-31 TLINTRSUM Register Bit Definitions (Continued) Name Bit(s) Type Function <11:7> R, 0 IPL14 Interrupts. Indicator of outstanding inter- IPL14_INTR rupts at IPL14. If a bit is set in this field, it indicates that there is at least one interrupt outstanding at IPL17 from the node number associated with the bit.

  • Page 286: Tlcon00,01,10,11-Console Communications Regs

    TLCON00,01,10,11—Console Communications Regs Address BB + 1200 & 1400; BB + 1300 & 1440 Access Two 32-bit wide register scratch pads are provided for each CPU on a module for communications between CPUs. Bits in these two registers are not allocated to any particular function and are un- der software control.

  • Page 287: Tlcon0A,0B,0C,1A,1B,1C-Diga Comm. Test Regs

    TLCON0A,0B,0C,1A,1B,1C—DIGA Comm. Test Regs Address BB + 1240, 1280, & 12C0; BB + 1340, 1380, & 13C0 Access DIGA Communications Test registers are used by diagnostic self- test code only. DIGA Communications Test Reg 0 DIGA Communications Test Reg 1 BXB-0724-94 The Console Communications registers are implemented in DIGA0.

  • Page 288: Rm_Range_Na,B-Memory Channel Range Regs

    RM_RANGE_nA,B—Memory Channel Range Regs Address BB + 1E00 through 1EC0 Access The Memory Channel Range registers define the two separate memory ranges to be set up on the CPU module. 31 30 28 2 7 RSVD BASE_ADR_A <39:20> RSVD RSVD BASE_ADR_B <39:20>...

  • Page 289: Memory Channel Range Register Bit Definitions

    Table 7-32 Memory Channel Range Register Bit Definitions Name Bit(s) Type Function <31> R/W, 0 Valid. When set, the contents of this register VALID are valid. <30:27> R/W, 0 Reserved. Read as zeros. RSVD <26:8> R/W, 0 Base Address <38:20>. The address of Mem- BASE_ADR<38:20>...

  • Page 290: Tldmcmd-Data Mover Command Register

    TLDMCMD—Data Mover Command Register Address BB + 1600 Access The TLDMCMD register controls the data mover transactions. 31 30 29 17 16 15 14 13 12 11 10 RSVD RSVD CPU_ID IN_PROG DM_8KB RSVD DM_DONE DM_4KB RM_INTLV DM_2KB RM_4 DM_1KB RM_3 DM_512B DM_CMD_VALID...

  • Page 291: Tldmcmd Register Bit Definitions

    Table 7-33 TLDMCMD Register Bit Definitions Name Bit(s) Type Function <31> W1C, 0 Data Movement Done. When set, indicates that DM_DONE the required function has been completed and that the data mover is idle. This bit clears when the CPU that initiated the data mover transaction writes one to it.
  • Page 292 Table 7-33 TLDMCMD Register Bit Definitions (Continued) Name Bit(s) Type Function <9:8> R/W, 0 Data Mover Command. Encodes the data mover DM_CMD command. <DM_CMD> Encoding Initialize memory at the addresses specified by the TLDMADRA register and the data length field to zero. Read blocks from addresses specified by the TLDMADRA register and the data length field.

  • Page 293: Tldmadra-Data Mover Source Address Register

    TLDMADRA—Data Mover Source Address Register Address BB + 1680 Access The TLMADRA register contains the source address of the data mover transaction. 31 30 29 SRC_ADR <38:9> BXB-0772-93 RSVD Table 7-34 TLDMADRA Register Bit Definitions Name Bit(s) Type Function <31:30> W, 0 Reserved.

  • Page 294: Tldmadrb-Data Mover Destination Address Reg

    TLDMADRB—Data Mover Destination Address Reg Address BB + 16C0 Access The TLMADRB register contains the destination address of the data mover transaction. 31 30 29 DEST_ADR <38:9> BXB-0771-93 RSVD Table 7-35 TLDMADRB Register Bit Definitions Name Bit(s) Type Function <31:30> R/W, 0 Reserved.

  • Page 295: Gbus$Whami

    GBUS$WHAMI Address FF C000 0000 Access The GBUS$WHAMI register provides node ID, CPU number, and reflects the status of some backplane signals. MFG_MODE_L CPU_NUM TLSB_CONWIN TLSB _BAD BXB-0514-93 Table 7-36 GBUS$WHAMI Register Bit Definitions Name Bit(s) Type Function <7> Reserved. Reads as zero. RSVD <6>...

  • Page 296: Gbus$Led0,1,2

    GBUS$LED0,1,2 Address FF C100 0000, FF C200 0000, FF C300 0000 Access The GBUS$LEDn registers are used by diagnostics to indicate test numbers for both CPUs. LEDs are illuminated by writing a one to the appropriate bits in one of the GBUS$LEDn registers. GBUS$LED0 is for CPU0 and drives a 7-segment display.

  • Page 297: Gbus$Miscr

    GBUS$MISCR Address FF C400 0000 Access The GBUS$MISCR register is used to gather various read bits that show module configuration. CONWIN1W RSVD CONWIN0W PROCNT DRIVE_CONWIN FPROM_WE DRIVE_RUN BXB-0725-93 System Registers 7-79...

  • Page 298: Gbus$Miscr Register Bit Definitions

    Table 7-37 GBUS$MISCR Register Bit Definitions Name Bit(s) Type Function <7> R, 0 Console Winner CPU1 Read. When set, indi- CONWIN1R cates that CPU1 is running console. This is a read copy of the write-only bit implemented in GBUS$MISCW. <6> R, 0 Console Winner CPU0 Read.

  • Page 299: Gbus$Miscw

    GBUS$MISCW Address FF C500 0000 Access The GBUS$MISCW register is used to gather write bits that control various functions. CONWIN1R CACSIZ: B-Cache Size CONWIN0R DRIVE_BAD RSVD TLSB_SECURE TLSB_RUN BXB-0515-93 Table 7-38 GBUS$MISCW Register Bit Definitions Name Bit(s) Type Function <7> W, 0 Console Winner CPU1 Write.

  • Page 300: Gbus$Tlsbrst

    GBUS$TLSBRST Address FF C600 0000 Access The GBUS$TLSBRST register is used to initiate a system reset se- quence. When this register is loaded with any value, the CCL RE- SET signal is asserted by the CPU module for 128 TLSB cycles. The CCL then drives TLSB_RESET for 16 µs.

  • Page 301: Gbus$Sernum

    GBUS$SERNUM Address FF C700 0000 Access The GBUS$SERNUM register is used to read and write an SROM on the clock module where the system serial number is stored. All reads and writes to this register are done by software. PIUA SROM_CLK PIUB RCV_DATA...
  • Page 302 Table 7-39 GBUS$SERNUM Register Bit Definitions (Continued) Name Bit(s) Type Function <4:3> R/W, 0 Expander Select. Selects which cabinet the EXPSEL power supply UART lines are logically connected to and, therefore, which set of three 48V power sup- plies are connected to the PS lines. May be used by console when TLDIAG<FRIGN>...

  • Page 303: Memory-Specific Registers

    7.5 Memory-Specific Registers Table 7-40 lists the memory-specific registers. Descriptions follow. Refer to Table 7-2 for the TLSB registers implemented on the memory module. Table 7-40 Memory-Specific Registers Address Mnemonic Register Name (Byte Offset) Serial EEPROM Control/Data Register + 01800 SECR Memory Interleave Register BB + 01840...

  • Page 304: Secr-Serial Eeprom Control/Data Register

    SECR—Serial EEPROM Control/Data Register Address BB + 0000 1800 Access The SECR register is used to access the EEPROM on the memory module. Access to the EEPROM is accomplished by continual up- dates of this register by software. RSVD SCLK XMT_SDAT RCV_SDAT BXB-0729-94...

  • Page 305: Mir-Memory Interleave Register

    MIR—Memory Interleave Register Address BB + 0000 1840 Access The MIR register is used by memory to determine DRAM RAS se- lection based upon how a given memory module is configured on the TLSB. Console software initializes this register upon start-up after system or node reset.

  • Page 306: Mir Register Bit Definitions

    Table 7-42 MIR Register Bit Definitions Name Bit(s) Type Function <31> R/W, 0 Valid. When set, enables the module to re- VALID spond to TLSB memory space transactions. <30:3> Reserved. Read as zero. RSVD <2:0> R/W, 0 Interleave. The value of this field loaded by INTLV console during system initialization determines whether this module is 1,2,4,8 or 16-way inter-...

  • Page 307: Mcr-Memory Configuration Register

    MCR—Memory Configuration Register Address BB + 0000 1880; BSB + 0000 1880 Access The MCR register provides information about the DRAM array structure including DRAM type and number of strings installed. It includes a battery OK indication and battery disable when used with the SRAM option.

  • Page 308: Mcr Register Bit Definitions

    Table 7-43 MCR Register Bit Definitions Name Bit(s) Type Function <31> R, none Battery OK. Indicates the state of the batteries when memory is configured to support the SRAM (NVRAM) option. When set, the battery supply is sufficient and present. When clear, two possibilities exist.
  • Page 309 Table 7-43 MCR Register Bit Definitions (Continued) Name Bit(s) Type Function <9> R, X Option Installed. This field specifies whether OPTION the SRAM option or the DRAM option is in- stalled. When read as a value of zero, the SRAM is installed.
  • Page 310 Table 7-43 MCR Register Bit Definitions (Continued) Name Bit(s) Type Function <5:4> R/W, 0 DRAM Timing Rate. This field is used to mod- ify the DRAM timing and refresh rate. At reset, DRAM timing defaults to supporting a 10 ns bus cycle time, while the refresh rate defaults to sup- porting a 30 ns bus.

  • Page 311: Stair-Self-Test Address Isolation Register

    STAIR—Self-Test Address Isolation Register Address BB + 0000 18C0 Access The STAIR register is used to isolate self-test failures to a given ad- dress segment or segments in the case of multiple failures in a module. This register breaks up a memory module into at most 32 distinct address segments, which would be the case of a 2-Gbyte module.

  • Page 312: Stair Register Bit Correspondence Of Memory Address Segments

    Table 7-45 STAIR Register Bit Correspondence of Memory Address Segments Bit Set Failing Address Range Bit Set Failing Address Range 0000 0000 – 03FF FFFF 4000 0000 – 43FF FFFF 0400 0000 – 07FF FFFF 4400 0000 – 47FF FFFF 0800 0000 –...

  • Page 313: Ster-Self-Test Error Register

    STER—Self-Test Error Register Address BB + 0000 1900 Access The STER register contains address information pertaining to data mismatch failures while self-test executes in POEM (pause on er- ror) mode. The contents of this register when read after an error has been detected in POEM mode can be used to isolate the failing DRAM string and to indicate which of the four MDIs the error was detected in.

  • Page 314: Ster Register Bit Definitions

    Table 7-46 STER Register Bit Definitions Name Bit(s) Type Function <31:8> Reserved. Read as zero. RSVD <7> W1C, 0 Self-Test Error in MDI3. Set during POEM mode when STE3 MDI3 detects a data mismatch error. The setting of this bit locks bit <6> (STE2), bit <5> (STE1), bit <4> (STE0), and bits <2:0>...

  • Page 315: Mer-Memory Error Register

    MER—Memory Error Register Address BB + 0000 1940 Access The MER register provides the DRAM string that failed when an ECC error is detected during a memory read transaction. This in- formation in conjunction with the error syndrome registers can be used to isolate correctable ECC errors down to a failing DRAM component.

  • Page 316: Mdra-Memory Diagnostic Register A

    MDRA—Memory Diagnostic Register A Address BB + 0000 1980 Access MDRA register A is used by diagnostics and manufacturing to force error conditions in the memory module and isolate failures. 31 30 29 28 27 RSVD DEDA: TLSB Data Err Dis POEMC: Pause on Err Mode Cont POEM: Pause on Err Mode FRUN: Free Run...
  • Page 317 Table 7-48 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function <29:28> R/W, 01 Refresh Rate. Determines the refresh rate of the module. <RFR> Refresh Rate 2X (Default) Reserved <27:9> Reserved. Read as zero. RSVD DEDA <8> R/W, 01 TLSB_DATA_ERROR Disable. When set and used in conjunction with POEM or FRUN modes, TLSB_DATA_ERROR will not assert if an error is detected.
  • Page 318 Table 7-48 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function <6> R/W, 01 Pause on Error Mode. When set, self-test will POEM halt execution upon the detection of a data mis- match error. TLSB_DATA_ERROR is asserted and remains asserted providing that <DEDA> is cleared, until either <POEM>...
  • Page 319 Table 7-48 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function <2> R/W, 0 Force Column Address Parity Error. When FCAPE set, incorrect DRAM column address parity is written into the addressed location when a match is detected between the TLSB address and the MDRB register and when <AMEN>...

  • Page 320: Mdrb-Memory Diagnostic Register B

    MDRB—Memory Diagnostic Register B Address BB + 0000 19C0 Access Memory Diagnostic Register B contains a 32-bit 64-byte aligned ad- dress value that is directly compared to TLSB_ADR<37:6>, or an address generated by the self-test address generator. The value loaded into this register is used in conjunction with MDRA and DDR0:3 to cause a specific data bit and/or check bit to be flipped whenever a TLSB memory write address matches the value con- tained in this register.

  • Page 321: Stdera,B,C,D,E-Self-Test Data Error Registers

    STDERA,B,C,D,E—Self-Test Data Error Registers Address BB + 0001 0000 to 0001 C100 Access The four sets of STDERx_n registers are used to isolate self-test failures down to a single failing bit or bits. When self-test is exe- cuted any data bit error(s) that are detected by the self-test data compare logic will set the appropriate data bit(s) in these regis- ters.

  • Page 322: Stder A, B, C, D Register Bit Definitions

    Table 7-50 STDER A, B, C, D Register Bit Definitions Name Bit(s) Type Function <31:0> R/W, 0 Self-Test Data Error Register_A. One or STDERA more bits set indicate a self-test data bit error. The contents of this register can be used to iso- late self-test failures to a single failing bit.

  • Page 323: Stdere Register Bit Definitions

    Table 7-51 STDERE Register Bit Definitions Name Bit(s) Type Function <31:19> Reserved. Read as zero. RSVD <18:16> R, X Valid Residue Check. This 3-bit read-only field is loaded at the beginning of the third pass in self-test and specifies which one of eight val- ues will be used by the self-test data-checking logic to determine that the self-test data linear feedback shift register logic is working correctly.

  • Page 324: Ddr0:3-Data Diagnostic Registers

    DDR0:3—Data Diagnostic Registers Address BB + 0001 0140; 0001 04140; 0001 8140; 0001 C140 Access There are four DDR registers, one in each of the four MDI ASICs. They are used by diagnostics and manufacturing to force error conditions, to isolate failures, and to margin the DC to DC power converters.
  • Page 325 Table 7-52 DDRn Register Bit Definitions (Continued) Name Bit(s) Type Function <15> R/W, 0 Enable Flip Data Bit. When set in conjunction EFLPD with MDRA<AMEN>, the data bit selected in DFLP<13:8> is flipped during memory write transactions. This function allows diagnostics to check ECC error detection logic.
  • Page 326 Table 7-52 DDRn Register Bit Definitions (Continued) Name Bit(s) Type Function <2> R/W, 0 Inhibit Clear on Free Run. When set in con- ICFR junction with MDRA<FRUN>, the contents of the STDER registers accumulate errors detected by self-test. When ICFR is cleared, the contents of the STDER registers will be cleared when self- test reenters the start execution phase due to <FRUN>...

  • Page 327: I/O Port-Specific Registers

    7.6 I/O Port-Specific Registers The I/O port responds to all addresses within its node space. If, however, the I/O port receives a read to a nonimplemented CSR, the I/O port returns Unpredictable data, with good ECC. Table 7-53 shows the mapping of the I/O port-specific registers.

  • Page 328: Rmrr0-1-Memory Channel Range Registers

    RMRR0-1—Memory Channel Range Registers Address BB + 1E00 to 1EC0 Access The I/O port houses two incoming Memory Channel address range register pairs. These register pairs are not specific to a single hose, but are generic across all four hoses. The I/O port compares the addresses of all incoming DMA write packets to the contents of these registers, regardless of the originating Up Hose.

  • Page 329: Rmrr0-1 Register Bit Definitions

    Table 7-54 RMRR0-1 Register Bit Definitions Name Bit(s) Type Function <31> R/W, 0 Valid. When set, the contents of this register VALID is valid. <30:28> R/W, 0 Reserved. Read as zeros. RSVD <27:8> R/W, 0 Base Address <39:20>. The address of Mem- BASE_ADR<38:20>...

  • Page 330: Iccmsr-I/O Control Chip Mode Select Register

    ICCMSR—I/O Control Chip Mode Select Register Address BB + 2000 Access The ICCMSR register can be used by software to select the desired mode of operation for the I/O port. RSVD SUP_CTL<1:0> ARB_CTL<1:0> BXB-0768-94 Table 7-55 ICCMSR Register Bit Definitions Name Bit(s) Type...
  • Page 331 Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function <3:2> R/W, 0 Suppress Control. This field can be pro- SUP_CTL<1:0> grammed to select the number of outstanding transactions the I/O port will permit on the TLSB before it asserts TLSB_ARB_SUP. No node, including the I/O port, may arbitrate for the TLSB address bus until TLSB_ARB_SUP is deasserted.
  • Page 332 Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function <3:2> R/W, 0 SUP_CTL<1:0> SUP_CTL Function Suppress after 2 transactions. If the I/O port detects 2 outstanding transactions pending on the TLSB, it asserts TLSB_ARB_ SUP during the command/ ad- dress cycle of the second transac- tion for one cycle, then deasserts it for one cycle.
  • Page 333 Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function <1:0> R/W, 0 ARB_CTL<1:0> ARB_CTL Function If the I/O port does not issue a 00 (Cont) back-to-back request to the same memory bank, that is, at least one potential request cycle to that memory bank occurs, then the next request to that memory bank by the I/O port can be initiated...
  • Page 334 Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function <1:0> R/W, 0 ARB_CTL<1:0> ARB_CTL Function Toggle 50% high/50% low mode. The I/O port always arbitrates on TLSB_REQ8_HIGH once, fol- lowed by TLSB_REQ8_LOW once for a given memory bank. This guarantees that the I/O port wins that memory bank at least 50% of the time.

  • Page 335: Iccnse-I/O Control Chip Node-Specific Error Reg

    ICCNSE—I/O Control Chip Node-Specific Error Reg Address BB + 2040 Access The ICCNSE register logs the collective error information relative to the internal operations of the I/O port. The following errors leave the I/O port in an Unpredictable state. If any of these errors occur, the I/O port should be reset to initial- ize it to a predictable state.

  • Page 336: Iccnse Register Bit Definitions

    Table 7-56 ICCNSE Register Bit Definitions Name Bit(s) Type Function <31> R/W, 0 Interrupt on NSES. When set, globally en- INTR_NSES ables all error interrupt sources on the I/O port. If an error is detected and this bit is set, the I/O port posts a level 17 interrupt to the CPU.
  • Page 337 Table 7-56 ICCNSE Register Bit Definitions (Continued) Name Bit(s) Type Function <26:25> W1C, 0 Up Vortex Error. This field is a composite UP_VRTX_ERR error field of possible Up Turbo Vortex errors that the ICR gate array can detect. There are two separate Up Turbo Vortex buses, one for hose<3:2>...
  • Page 338 Table 7-56 ICCNSE Register Bit Definitions (Continued) Name Bit(s) Type Function <22> W1C, 0 Multiple Interrupt Error. The I/O port has MULT_INTR_ERR four TLILID FIFOs, one for each IPL. Each TLILID FIFO is four entries deep, so it can ac- cept up to four pending interrupts for the given IPL level.
  • Page 339 Table 7-56 ICCNSE Register Bit Definitions (Continued) Name Bit(s) Type Function <15:12> W1C, 0 Up Hose Packet Error. This field indicates UP_HOSE_PKT_ERR that one of the Up HDR gate arrays detected either an illegal command or sequence error on the corresponding Up Hose. An IPL17 interrupt is generated when these bits set if interrupts are enabled by INTR_NSES (ICCNSE<31>).

  • Page 340: Iccdr-I/O Control Chip Diagnostic Register

    ICCDR—I/O Control Chip Diagnostic Register Address BB + 2080 Access The ICCDR register can be programmed by diagnostics to force er- rors on the TLSB and Turbo Vortex buses for the I/O port to detect. Hose errors can also be forced, but this is a function of the loopback feature.

  • Page 341: Iccdr Register Bit Definitions

    Table 7-57 ICCDR Register Bit Definitions Name Bit(s) Type Function <31> R/W, 0 Enable DMA Hose ID. When set and the I/O ENA_DMA_HID port is hard-wired to enable debug mode, the number of the hose that originated the transac- tion is inserted at address bits <26:25> for mem- ory transactions (that is, A<28>=0).
  • Page 342 Table 7-57 ICCDR Register Bit Definitions (Continued) Name Bit(s) Type Function <4> R/W, 0 Disable TLSB Fault. Setting this bit prevents DIS_TLSB_FAULT the I/O port from driving TLSB_FAULT even if a system fatal error condition is detected by the I/O port. It allows diagnostics to force various fatal TLSB errors (such as APE, ATCE, BBE, DTO, DSE) and various fatal Up Turbo Vortex errors without crashing the system.

  • Page 343: Iccmtr-I/O Control Chip Mailbox Transaction Reg

    ICCMTR—I/O Control Chip Mailbox Transaction Reg Address BB + 20C0 Access The ICCMTR register indicates if a mailbox transaction is in pro- gress and the targeted hose of the transaction. This register is physically located in the ICR gate array. RSVD MBX_TIP<3:0>...

  • Page 344: Iccmtr Register Bit Definitions

    Table 7-58 ICCMTR Register Bit Definitions Name Bit(s) Type Function <31:4> Reserved. Read as zeros. RSVD <3:0> W1C, 0 Mailbox Transaction in Progress. Indicates MBX_TIP<3:0> that the I/O port has transmitted a Mailbox Command packet, targeting the corresponding hose, across one of the Down Turbo Vortex buses.

  • Page 345: Iccwtr-I/O Control Chip Window Transaction Reg

    ICCWTR—I/O Control Chip Window Transaction Reg Address BB + 2100 Access The ICCWTR register indicates if a window transaction is in pro- gress and the targeted hose of the transaction. This register is physically located in the ICR gate array. RSVD WIP<3:0>...

  • Page 346: Idpnse0-3-I/O Data Path Node-Specific Error Regs

    IDPNSE0–3—I/O Data Path Node-Specific Error Regs Address BB + 2A40, 2140, 2240, 2340 Access The IDPNSE0–3 registers are physically located in the correspond- ing IDR0–3 I/O port gate arrays. They log the collective error infor- mation related to the internal operations of the gate arrays. The following errors leave the I/O port in an Unpredictable state.

  • Page 347: Idpnse0-3 Register Bit Definitions

    Table 7-60 IDPNSE0–3 Register Bit Definitions Name Bit(s) Type Function <31> W, 0 HOSEn Reset. When this bit is written to a HOSEn_RESET one, the I/O port generates a reset to the associ- ated hose as follows: HOSEn_RESET in IDPNSE3 causes a reset to be generated to HOSE 3 HOSEn_RESET in IDPNSE2 causes a reset to be generated to HOSE 2...
  • Page 348 Table 7-60 IDPNSE0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function <26:25> W1C, 0 IDR Up Vortex Error. This is a composite er- IDR_UP_VRTX_ERR ror field of possible Up Turbo Vortex errors that the IDR gate arrays can detect in each of the IDR0-3 data path gate arrays as follows: IDR_UP_VRTX_ERR<1:0>...
  • Page 349 Table 7-60 IDPNSE0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function <3> W1C, X HOSEn Power OK Transitioned. This bit is HOSEn_PWROK_TR latched whenever the associated HOSEn_ PWROK signal transitions. HOSEn_PWROK can then be read to determine the reason why this bit set.
  • Page 350 Table 7-60 IDPNSE0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function <1> R, X HOSEn Power OK. This bit is derived from HOSEn_PWROK the HOSEn_PWROK signal and reflects its cur- rent level. If the associated hose cable is con- nected properly to the I/O adapter and has suffi- cient power to process commands, then this bit will be a 1.

  • Page 351: Idpdrn-I/O Data Path Diagnostic Registers

    IDPDRn—I/O Data Path Diagnostic Registers Address BB + 2A80, 2180, 2280, 2380 Access The IDPDRn registers can be programmed by diagnostics to force errors on the TLSB and Turbo Vortex buses for the I/O port to de- tect. System bus errors are transmitted on the TLSB and are de- tected by the I/O port when the signals are received back.

  • Page 352: Idpdr0-3 Register Bit Definitions

    Table 7-61 IDPDR0–3 Register Bit Definitions Name Bit(s) Type Function <31> R/W, 0 Voltage Margin. When set, the module’s 5.0 VOLT_MARG and 3.35 volt DC to DC converters are margined over a +/− 5% range. IDR Register Voltage Margin IDPDR0 −5% IDPDR1 3.5.
  • Page 353 Table 7-61 IDPDR0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function <19> R/W, 0 Force Down Valid Sequence Error. When FRC_VAL_SEQ_ERR set, forces VALID to be asserted for an extra cycle for down Turbo Vortex Mailbox Command packets. <18> R/W, 0 Force Down Data Parity Error.

  • Page 354: Error Matrix For Force Error Bits

    Table 7-62 Error Matrix for Force Error Bits Set Diagnostic Bit Perform Transaction Detect Error Write to CSR in IDR1 IDPNSE1<IDR_CSR_BUS_PE> IDPDR0<FRC_CSR_BUS_DPE> Write to CSR in IDR2 IDPNSE2<IDR_CSR_BUS_PE> IDPDR0<FRC_CSR_BUS_DPE> Write to CSR in IDR3 IDPNSE3<IDR_CSR_BUS_PE> IDPDR0<FRC_CSR_BUS_DPE> Write to CSR in ICR ICCNSE<ICR_CSR_BUS_PE>...

  • Page 355: Idpvr-I/O Data Path Vector Register

    IDPVR—I/O Data Path Vector Register Address BB + 2B40 Access The IDPVR register is loaded by software with the vector associ- ated with I/O port-specific errors. 16 15 VECTOR<15:0> RSVD BXB-0759-93 Table 7-63 IDPVR Register Bit Definitions Name Bit(s) Type Function <31:16>...

  • Page 356: Idpmsr-I/O Data Path Mode Select Register

    IDPMSR—I/O Data Path Mode Select Register Address BB + 2B80 Access The IDPMSR register can be used by software to select the desired mode of operation for the I/O port. RSVD HDR_LPBCK_EN ENA_HOSE_VECT BXB-0761-94 7-138 System Registers...

  • Page 357: Idpmsr Register Bit Definitions

    Table 7-64 IDPMSR Register Bit Definitions Name Bit(s) Type Function <31:2> R/W, 0 Reserved. Read as zeros. RSVD <1> R/W, 0 HDR Loopback Enable. When set, enables HDR_LPBCK_EN the I/O port to internally loopback Mailbox Command packets and Sparse Window Read packets between the Down Hose and Up Hose.

  • Page 358: Ibr-Information Base Repair Register

    IBR—Information Base Repair Register Address BB + 2BC0 Access The IBR register is used to access the EEPROM located on the I/O port. To access the EEPROM, software continually updates the IBR register to transfer command, address, and data to and from the device.

  • Page 359: Ibr Register Bit Definitions

    Table 7-65 IBR Register Bit Definitions Name Bit(s) Type Function <31:3> R/W, 0 Reserved. Read as zeros. RSVD <2> R/W, 0 Serial Clock. Used to implement the SCLK FEPROM serial clock interface by software. When this bit is written with a one, the FEPROM serial clock input is forced to a logic high.

  • Page 360: Kftia Specific Registers

    7.7 KFTIA Specific Registers Registers specific to the integrated I/O module, the KFTIA (registers in ad- dition to those specific to the KFTHA module) can be grouped in two classes: • PCIA registers • PCI device registers The discussion of these registers is beyond the scope of this manual. PCIA registers are discussed in the DWLPA PCI Adapter Technical Manual.

  • Page 361: Chapter 8 Interrupts

    Chapter 8 Interrupts The TLSB supports both vectored and nonvectored interrupts. • Vectored interrupts are the traditional I/O adapter interrupts, where the processor dispatches the interrupt based on an IDENT (identifica- tion) vector supplied by the adapter. The value of the IDENT vector is loaded into each adapter at system initialization.

  • Page 362: Cpu Interrupt Rules

    CSR read data (passive release). 8.1.2 CPU Interrupt Rules Both AlphaServer 8200 and 8400 systems support up to three I/O modules. Each I/O module can generate four interrupts at level 0, four at level 1, four at level 2, and five at level 3. Thus, one I/O port can have 17 out- standing interrupts.

  • Page 363: Nonvectored Interrupts

    • The targeted CPUs are interrupted at an appropriate level and the CPU issues a CSR read transaction over the TLSB bus to the TLILIDn register for the relevant interrupt level to get the interrupt vector. • After the CSR read of TLILIDn is successfully completed, the I/O mod- ule considers the interrupt to be serviced.

  • Page 364: Virtual Node Identification - Tlvid

    Refer to Chapter 7 for the format of all registers used in the interrupt op- eration. 8.3.1.1 Virtual Node Identification - TLVID TLSB system functionality requires that certain units be identified uniquely, independent of physical location in the system. Specifically, indi- vidual memory banks and CPUs must be uniquely addressable entities at the system level, independent of their physical node ID.

  • Page 365: Generating Interrupts

    only to TLIOINTR4. Interrupts at the IPL level(s) specified in bits <19:16> are targeted at the VIDs specified in bits <15:0> (see Chapter 7). 8.3.2 Generating Interrupts The TLCPUMASK for each I/O port and the TLINTRMASK for each CPU are set up by the console. To generate an interrupt, the I/O port issues a write to its corresponding TLIOINTRn register in TLSB broadcast space.

  • Page 366: Module-Level Interrupts

    TLIPINTR register and interrupts either (or both) of the CPUs as appro- priate, based on their virtual node IDs. The interprocessor interrupt is cleared by a write to TLINTRSUM<IP>. 8.3.5 Module-Level Interrupts The CPU module uses the hardware interrupts provided as shown in Table 8-1.
  • Page 367 Glossary Address gate array. Bank Smallest group of DRAMs that can be interleaved. A bank consists of one or more strings. Block 64 bytes of data within naturally aligned boundaries. Control address interface. DRAM data bus. The 576-bit bidirectional data bus that interfaces be- tween the DRAM chips and the MDC gate arrays.
  • Page 368 Fast, narrow, single-ended. Fast, wide, differential. Internal Hose The connection (etch pathway) between the TLSB interface and the inte- grated I/O section of the KFTIA. HDR (DC296) Hose to I/O data path chip. Hose The interface between the I/O port and a single I/O bus adapter module. ICR (DC295) I/O control chip.
  • Page 369 TLSB The system bus for Digital AlphaServer 8200 and 8400 systems. Turbo Vortex bus The bus that interconnects the HDR, IDR, and ICR chips.
  • Page 371 Index Address bus request, 2-13 Address bus sequencing, 2-11 ABTCE, 7-8 Address bus transactions, 2-12 Accessing remote I/O CSRs, 6-15 Address Bus Transmit Check Error bit, 7-8 Accessing through I/O window space, 6-15 Address decode, 2-10 Accessing through mailboxes, 6-14 Address Extent bits, 7-71 Access, remote I/O CSR, 6-14 Address Mask bits, 7-22...
  • Page 372 A2MAPE1, 7-61 states, 4-4 state changes, 4-5 B-Cache Idle Time bits, 7-53 B-Cache Size bit, 7-53 Backup cache, 1-4, 4-2 B-Cache Size bits, 7-80 BAE, 7-12 B-cache states, 4-4 BANKV, 7-24 B-cache tags, 4-3 Bank address decoding, 2-9 Bank available flags, 5-4 Bank available status, 2-11 Bank available transition, 2-14 Cache...
  • Page 373 Correctable Read Data Error bit, 7-9 CSR bank contention, 2-15 Correctable Read Data Error Interrupt Disable CSR bus parity errors, 6-77 bit, 7-18 CSR interface context, 5-13 Correctable Read ECC Error bit, 7-27 CSR interface, memory, 5-13 Correctable Write Data Error bit, 7-9 CSR multiplexing, memory, 5-16, 5-17 Correctable Write Data Error Interrupt CSR reads to remote I/O, 2-32...
  • Page 374 Data return format, 2-19 Disable Refresh bit, 7-98 Data status errors, 2-41, 6-73 Disable TLSB Command Transmission bit, Data Status Error bit, 7-8 7-124 Data Syndrome 0 bit, 7-9 Disable TLSB Fault bit, 7-124 Data Syndrome 1 bit, 7-9 Distributed arbitration, 2-12 Data Syndrome 2 bit, 7-9 DIS_DN_HOSE_RST, 7-134 Data Syndrome 3 bit, 7-9...
  • Page 375 Drive TLSB Bad bit, 7-81 EFLPD, 7-107 DRIVE_BAD, 7-81 Enable DMA Hose ID bit, 7-123 DRIVE_CONWIN, 7-81 Enable Flip Data bit, 7-107 DRIVE_RUN, 7-81 Enable Flip ECC Check bit, 7-107 DSE, 7-8 Enable Hose onto Vector bit, 7-139 DS0, 7-9 ENA_DMA_HID, 7-123 DS1, 7-9 ENA_HOSE_VECT, 7-139...
  • Page 376 False arbitration, 2-7, 2-14 Gbus Slow bit, 7-47 Fatal Data Transmit Check Error bit, 7-8 Gbus space, 3-9 Fatal No Acknowledge Error bit, 7-10 Gbus Timeout Error bit, 7-58 Fault Disable bit, 7-52 GBUS$LED register, 7-78 FAULT_DIS, 7-52 GBUS$MISCR register, 7-79 FBANK, 7-25 GBUS$MISCW register, 7-81 FCAPE, 7-101...
  • Page 377 ICCNSE register, 7-117 Interrupt generation, 8-5 ICCWTR register, 7-127 Interrupt Level bits, 7-36 ICC and IDP internal illogical errors, 6-77 Interrupt Level IDENT registers, 7-30 ICC CSR Bus Par Err bit, 7-118 Interrupt Mask register, 7-63 ICC Internal Error bit, 7-118 Interrupt on NSES bit, 7-118 ICFR, 7-108 Interrupt operation, I/O port, 8-2...
  • Page 378 I/O Control Chip Node-Specific Error register, 7-117 MADR, 7-102 I/O Ctrl Chip Window Transaction register, Mailboxes, 2-30 7-127 Mailbox Address bits, 7-32 I/O Data Path Diagnostic register, 7-133 Mailbox Command packet, 6-41, 6-42 I/O Data Path Node Specific Error register, Mailbox data structure, 2-30, 2-31, 7-33 7-128 Mailbox Pointer register, 7-32...
  • Page 379 Memory mapping register error, 3-18, 6-71 OpenVMS, 1-7 Memory Mapping Register Error bit, 7-10 Operation completion status, 7-34 memory module capacity, 7-105 OPTION, 7-91 Memory module, overview, 1-4 Option Installed bit, 7-91 Memory organization, 4-13 Memory refresh, 4-16 Memory sections, 4-10 Packet specifications, Down Hose, 6-39 Memory self-test, 4-16 Packet specifications, Up Hose, 6-52...
  • Page 380 CPU Module Configuration, 7-52 SCSI, 7-142 Data Diagnostic, 7-106 TLBER, 7-7 Data Mover Command, 7-72 TLCNR, 7-14 Data Mover Destination Address, 7-76 TLDEV, 7-5 Data Mover Source Address, 7-75 TLILID0-3, 7-30 Diagnostic Setup, 7-47 TLIOINTR4-8, 7-36 DIGA Communications Test, 7-69 TLIPINTR, 7-35 DIGA Error, 7-57 TLMCR, 7-43...
  • Page 381 Self-Test Error in MDI0 bit, 7-96 STAIR register, 7-93 Self-Test Error in MDI1 bit, 7-96 STATUS, 7-34 Self-Test Error in MDI2 bit, 7-96 STDERA, 7-104 Self-Test Error in MDI3 bit, 7-96 STDERB, 7-104 Self-Test Error register, 7-95 STDERC, 7-104 Self-Test error reporting, 4-18 STDERD, 7-104 Self-Test Failing Address Range bits, 7-93 STDERE, 7-105...
  • Page 382 TLEPMERR register, 7-59 TLSB_ADR<39>, 6-17, 6-19, 6-21 TLEP_VMG register, 7-62 TLSB_ADR<4:0>, 6-19 TLESR0-3 registers, 7-26 TLSB_ADR<4:3>, 6-17 TLFADR0-1 registers, 7-24 TLSB_BAD, 7-77 TLILID0-3 registers, 7-30 TLSB_BANK_NUM<3:0>, 6-17, 6-19 TLINTRMASK register, 7-63 TLSB_BANK_NUM<<3:0>, 6-21 TLINTRSUM register, 7-65 TLSB_CONWIN, 7-77 TLIOINTR4-8 registers, 7-36 TLSB_DATA_ERR, 6-67 TLIPINTR register, 7-35 TLSB_DATA_ERROR Disable bit, 7-99...
  • Page 383 UECC, 7-27 Uncorrectable Data Error bit, 7-10 WDATA, 7-33 Uncorrectable ECC Error bit, 7-27 Window in Progress bits, 7-127 Unexpected acknowledge, 6-71 Window Space Decr Queue Counter registers, Unexpected Acknowledge bit, 7-8 7-38 Unexpected acknowledge error, 3-18 Window space I/O, 2-32 Unexpected mailbox status packet, 6-77 Window space mapping, dense, 6-37 Unexpected Mailbox Status Packet Received...

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