Tlsb Errors - DEC AlphaServer 8200 Technical Manual

predictable as the value has no significance. The I/O node may choose not
to acknowledge the command and save data bus cycles.
The I/O node proceeds to read the selected remote CSR. When the data is
available and there are no errors reading the data, the I/O node issues a
CSR write command to a CSR Read Data Return Data (TLRDRD) Register
in local CSR broadcast space. During this transaction it asserts the virtual
ID of the CPU that initiated the read transaction in the bank number field
and returns the read data. The TLRDRD register format is shown in Fig-
ure 2-7. The size and format of the data is implementation specific.
Figure 2-7 TLRDRD Register
511 0
READ_DATA (64 Bytes)
BXB-0541h-94
If an error is detected reading the remote CSR, the I/O node issues a CSR
write command to a CSR Read Data Return Error (TLRDRE) Register in
local CSR broadcast space. During this transaction it asserts the virtual
ID of the CPU that originated the read transaction in the bank number
field and returns Unpredictable data.
A single CPU may not have more than one outstanding window space CSR
read transaction pending at any given time. The only identification that is
returned with the read data is the CPU virtual ID. Data for outstanding
read commands may be returned in any order.
If the read transaction fails to complete after several seconds, the CPU
aborts the transaction through an implementation-specific timeout mecha-
nism.

2.4 TLSB Errors

The TLSB is designed to provide a high reliability electrical environment
for system bus operation. Consequently, error handling is biased toward
detection rather than correction. An attempt is made to retain state for
either PALcode or system software to determine the severity level and
recoverability of any error, and for hardware fault isolation to one module.
However, due to the deep pipelined nature of the protocol, the amount of
state saved is limited.
If there is any probability that the integrity of the system may have been
compromised, the bus interfaces immediately flag the processor to effect an
ordered crash, if possible. At any stage the bus error detection logic at-
tempts to identify any single failure event that would otherwise go unno-
ticed and result in erroneous continued system operation.
The system is not designed to detect multiple error occurrences. The only
exception is the data bus ECC, which permits single-bit, double-bit, and
some multiple-bit error detection in the DRAM memory, data bus, and
cache subsystems.
TLSB Bus 2-33