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4.1.3 Second-Level Cache
The second-level cache (S-cache) is a 96-Kbyte, 3-way set associative,
physically addressed, write-back, write-allocate cache with 32- or 64-byte
blocks (configured by SC_CTL<SC_BLK_SIZE>; see DECchip 21164 Func-
tional Specification). It is a mixed data and instruction cache. The S-
cache is fully pipelined.
If the S-cache block size is configured to 32 blocks, the S-cache is organized
as three sets of 512 blocks where each block consists of two 32-byte
subblocks. Otherwise, the S-cache is three sets of 512 64-byte blocks.
The S-cache tags contain the following special bits for each 32-byte
subblock: one dirty bit, one shared bit, two INT16 modified bits, and one
valid bit. Dirty and shared are the coherence state of the subblock re-
quired for the cache coherence protocol. The modified bits are used to pre-
vent unnecessary writebacks from the S-cache to the B-cache. The valid
bit indicates that the subblock is valid. In 64-byte block mode, the valid,
shared, and dirty bits in one subblock match the corresponding bits in the
other subblock.
The S-cache tag compare logic contains extra logic to check for blocks in
the S-cache that map to the same B-cache block as a new reference. This
allows the S-cache block to be moved to the B-cache (if dirty) before the
block is evicted because of the new reference missing in the B-cache.
The S-cache supports write broadcast by merging write data with S-cache
data in preparation for a write broadcast as required by the coherence pro-
tocol.
4.2 Backup Cache
The baseline design of the system supports two 4-Mbyte physically ad-
dressed direct-mapped B-caches per CPU module, one for each processor.
The B-cache is a superset of the DECchip 21164's D-cache and S-cache. I-
cache coherency is handled by software.
4.2.1 Cache Coherency
TLSB supports a conditional write update protocol. If a block is resident in
more than one module's cache (or in both caches on one module), the block
is said to be "shared." If a block has been updated more recently than the
copy in memory, the block is said to be "dirty." If a location in the direct-
mapped cache is currently occupied, the block is said to be "valid." The
Shared, Dirty, and Valid bits are stored (together with odd parity) in the
tag status RAMs.
The DECchip 21164 supports a write invalidate protocol that is a subset of
the conditional write update protocol. A read to a block currently in an-
other CPU's cache causes the block to be marked shared in both caches. A
write to a block currently in the cache of two or more CPUs causes the data
to be written to memory and the block to be invalidated in all caches ex-
cept in the cache of the CPU issuing the write.
4-2 Memory Subsystem
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