Table of Contents
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I/O Control Chip Node-Specific Error register,
7-117
I/O Ctrl Chip Window Transaction register,
7-127
I/O Data Path Diagnostic register, 7-133
I/O Data Path Node Specific Error register,
7-128
I/O Data Path Vector register, 7-137
I/O interrupt mechanism, 8-3
I/O Interrupt registers, 7-36
I/O port addressing, 6-14
I/O port arbitration, node 8, 6-31
I/O port block diagram, 6-3
I/O port components, 6-2
I/O port CSR read/write transactions, 6-28
I/O port errors, hard, 6-75
I/O port errors, hard internal, 6-66
I/O port errors, miscellaneous, 6-77
I/O port error handling, 6-66
I/O port generated error interrupts, 6-9
I/O port interrupt operation, 8-2
I/O port interrupt rules, 8-1
I/O port TLSB interface, 6-23
I/O port transactions, 6-3, 6-23
I/O port transaction types, 6-5
I/O port-specific registers, 7-109
I/O space, 3-8
I/O subsystem block diagram, 6-1
I/O window space, 3-8
read transactions, 6-29
transactions, 6-7
write transactions, 6-29
K
KFTIA block diagram, 6-79
KFTIA connections, 6-78
KFTIA overview, 6-78
KFTIA specific registers, 7-142
L
LKTO, 7-11
LKTOD, 7-17
Loadable diagnostic environment, 1-8
Lockout Enable bit, 7-53
LOCKOUT_EN, 7-53
Lock on First Error bit, 7-15
Lock on First Syndrome bit, 7-26
Lock registers, 4-6
LOE, 7-108
LOFE, 7-15
LOFSYN, 7-26
Look-back-two, 2-14, 6-34
Index-8
M
MADR, 7-102
Mailboxes, 2-30
Mailbox Address bits, 7-32
Mailbox Command packet, 6-41, 6-42
Mailbox data structure, 2-30, 2-31, 7-33
Mailbox Pointer register, 7-32
Mailbox status return, 6-52
Mailbox status return packet, 6-53, 6-54
Mailbox transactions, 6-5, 6-28, 6-84
Mailbox Transaction in Progress bits, 7-126
Main memory, 4-9
MAI CSR sequencer, 5-15
Manufacturing Mode Low bit, 7-77
Mapping, CSR address space, 7-2
Map RAM, 6-82
MARG, 7-106
Margin bit, 7-106
MASK, 7-33, 7-35
Match Address bits, 7-102
MBX, 7-32
MBX_TIP<3:0>, 7-126
MCR register, 7-89
MDI CSR functions, 5-16
MDI CSR sequencer, 5-16
MDI error detection and correction logic, 5-12
MDRA register, 7-98
MDRB register, 7-102
Memory address bit mapping, 2-7
Memory bank addressing scheme, 2-8
Memory bank address decoding, 2-9
Memory bank state machine, 5-2
Memory barriers, 4-9
Memory block diagram, 4-10
Memory Channel Decr Queue Counter register
X, 7-39
Memory Channel Decr Queue Counter register
8, 7-40
Memory Channel Interleave bit, 7-73
Memory Channel Operation TLSB_ADR<3>
bit, 7-73
Memory Channel Operation TLSB_ADR<4>
bit, 7-73
Memory Channel Range registers, 7-70, 7-110
Memory Channel Size bit, 7-53
Memory Channel Write packet, 6-53
Memory Channel Interleave Enable bit, 7-111
Memory Configuration register, 7-89
Memory Control register, 7-43
Memory data interface, 4-11, 5-9
Memory Diagnostic register A, 7-98
Memory Diagnostic register B, 7-102
Memory Error register, 7-97
Memory Interleave register, 7-87
Memory Mapping registers, 7-21
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