Tlsb Csr Address Mapping - DEC AlphaServer 8200 Technical Manual

Table 2-8

TLSB CSR Address Mapping

Address Name
BB+000 Device Register
Bus Error Register
BB+040
Configuration Register
BB+080
Virtual ID Register
BB+0C0
Memory Mapping Register
BB+200
BB+240 Memory Mapping Register
Memory Mapping Register
BB+280
Memory Mapping Register
BB+2C0
Memory Mapping Register
BB+300
Memory Mapping Register
BB+340
BB+380 Memory Mapping Register
Memory Mapping Register
BB+3C0
TLSB Failing Address Register 0
BB+600
TLSB Failing Address Register 1
BB+640
TLSB Error Syndrome Register 0
BB+680
TLSB Error Syndrome Register 1
BB+6C0
BB+700 TLSB Error Syndrome Register 2
TLSB Error Syndrome Register 3
BB+740
Interrupt Level0 IDENT Register
BB+A00
Interrupt Level1 IDENT Register
BB+A40
Interrupt Level2 IDENT Register
BB+A80
BB+AC0 Interrupt Level3 IDENT Register
CPU Interrupt Mask Register
BB+B00
1
Mailbox Pointer Register
BB+C00
Reserved for private transactions
BSB+000
IP Interrupt Register
BSB+040
I/O Interrupt Register
BSB+100
BSB+140 I/O Interrupt Register
I/O Interrupt Register
BSB+180
I/O Interrupt Register
BSB+1C0
I/O Interrupt Register
BSB+200
Window Space Decr Queue Counter Reg 4
BSB+400
BSB+440 Window Space Decr Queue Counter Reg 5
Window Space Decr Queue Counter Reg 6
BSB+480
Window Space Decr Queue Counter Reg 7
BSB+4C0
Window Space Decr Queue Counter Reg 8
BSB+500
Reflective Mem Decr Queue Counter Reg X
BSB+600
Reflective Mem Decr Queue Counter Reg 8
BSB+640
BSB+800 CSR Read Data Return Data Register
CSR Read Data Return Error Register
BSB+840
Memory Control Register
BSB+1880
1 Virtual CPU ID asserted on TLSB_BANK_NUM<3:0> to select one of 16 registers.
2 Data not to be recorded by another node.
Modules That
Mnemonic Implement
TLDEV CPU, Memory, I/O
TLBER CPU, Memory, I/O
TLCNR CPU, Memory, I/O
TLVID CPU, Memory
TLMMR0 CPU, I/O
TLMMR1 CPU, I/O
TLMMR2 CPU, I/O
TLMMR3 CPU, I/O
TLMMR4 CPU, I/O
TLMMR5 CPU, I/O
TLMMR6 CPU, I/O
TLMMR7 CPU, I/O
TLFADR0 CPU, Memory, I/O
TLFADR1 CPU, Memory, I/O
TLESR0 CPU, Memory, I/O
TLESR1 CPU, Memory, I/O
TLESR2 CPU, Memory, I/O
TLESR3 CPU, Memory, I/O
TLILID0 I/O
TLILID1 I/O
TLILID2 I/O
TLILID3 I/O
TLCPUMASK I/O
TLMBPR I/O
2
TLPRIVATE None
TLIPINTR CPU
TLIOINTR4 CPU
TLIOINTR5 CPU
TLIOINTR6 CPU
TLIOINTR7 CPU
TLIOINTR8 CPU
TLWSDQR4 CPU
TLWSDQR5 CPU
TLWSDQR6 CPU
TLWSDQR7 CPU
TLWSDQR8 CPU
TLRMDQRX CPU, I/O
TLRMDQR8 CPU, I/O
TLRDRD CPU
TLRDRE CPU
TLMCR Memory
TLSB Bus 2-29