Preface - DEC AlphaServer 8200 Technical Manual

Intended Audience
Document Structure
This manual is intended for developers of system software and for service
personnel. It discusses the AlphaServer 8200/8400 systems that are de-
signed around the DECchip 21164 CPU and use the TLSB bus as the main
communication path between all the system modules. The manual de-
scribes the operations of all components of the system: the TLSB bus,
CPU modules, memory modules, and the I/O modules. It discusses in de-
tail the functions of all registers in the system. When necessary, the man-
ual refers the reader to other documents for more elaborate discussions or
for specific information. Thus, the manual does not give the register files
of PCI bus devices but indicates sources where information can be found.
The manual assumes programming knowledge at machine language level
and familiarity with the OpenVMS Alpha and Digital UNIX (formerly
DEC OSF/1) operating systems.
The material is presented in eight chapters.
Chapter 1, Overview, presents an overall introduction to the server sys-
tem.
Chapter 2, TLSB Bus, describes the main communication path of the sys-
tem. It discusses the operations of the address bus and the data bus, CSR
addressing, and errors that can occur during bus transactions.
Chapter 3, CPU Module, describes the major components and operations
of the CPU module. It explains the CPU module's memory and I/O address
spaces, and gives a summary of the errors detected by the CPU module.
Chapter 4, Memory Subsystem, describes the structure of the memory
hierarchy from the system perspective. The memory hierarchy comprises
the DECchip 21164 internal cache, the second-level cache implemented on
the CPU chip, the backup cache implemented on the CPU module, and the
main memory that is implemented as a separate module and forms a node
on the TLSB bus. The chapter provides a discussion of the various ways
main memory can be organized to optimize access time.
Chapter 5, Memory Interface, describes the various components of the
memory module, the memory data interface, and how the CSR interface
manages the transfer of information between the TLSB bus and the TLSB
accessible memory module registers.
Chapter 6, I/O Port, describes the configuration of the I/O port and the
main components of the I/O subsystem (KFTHA and KFTIA modules). It
discusses addressing of memory and I/O devices and accessing of remote
I/O node CSRs through mailboxes and direct I/O window space. The

Preface

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