Tlintrmask0-1-Interrupt Mask Registers - DEC AlphaServer 8200 Technical Manual

TLINTRMASK0–1—Interrupt Mask Registers
Address BB + 1100, BB + 1140
Access R/W
The TLINTRMASK0–1 registers are used to enable interrupts to
the CPUs. TLINTRMASK0 controls interrupts on CPU0 and TLIN-
TRMASK1 on CPU1.
31
RSVD
Ctrl/P HALT ENA
HALT ENA
INTIM_ENA
IP_ENA
9 8 7 6 5 4 3 2
IPL17_ENA
IPL16_ENA
IPL15_ENA
IPL14_ENA
DUART0_ENA
BXB-0770-93
System Registers 7-63
1 0