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Table 7-56 ICCNSE Register Bit Definitions
Name
INTR_NSES
TLSB_WND_OFLO
ICR_CSR_BUS_PE
ICR_IE
7-118 System Registers
Bit(s)
Type
Function
<31>
R/W, 0
Interrupt on NSES. When set, globally en-
ables all error interrupt sources on the I/O port.
If an error is detected and this bit is set, the I/O
port posts a level 17 interrupt to the CPU. The
subsequent read of TLILID3 returns the vector
from the IDR Vector Register (IDPVR). When
this bit is clear, no interrupt is posted as the re-
sult of an I/O port detected error. The appropri-
ate error bit will still be set in ICCNSE or ID-
PNSE0–3, however. Note that all I/O port spe-
cific error bits must be cleared before a
subsequent error interrupt can be posted.
<29>
W1C, 0
TLSB Window Overflow. Set when the ICR
control gate array detects an overflow of its win-
dow transaction address FIFO. This occurs if
more than four window transactions occur on the
TLSB before the I/O port can perform a CSR
write to the Window Space Decrement Queue
Counter Register in broadcast space. This is a
fatal error that causes the I/O port to drive
TLSB_FAULT.
<28>
W1C, 0
ICR CSR Bus Parity Error. When set, indi-
cates that the ICR gate array detected a parity
error on the CSR data bus when receiving data
from the IDR0 gate array. An IPL 17 interrupt
will be generated when this bit sets if interrupts
are enabled by INTR_NSES (ICCNSE<31>).
<27>
W1C, 0
ICR Internal Error. When set, indicates that
the ICR gate array detected an illogical internal
error. The internal error generally indicates a
hardware problem where control logic encoun-
tered an undefined condition or conditions.
ICR_IE is a system fatal error that causes the
I/O port to assert TLSB_FAULT. The following
conditions cause the I/O port to assert ICR_IE:
Up Turbo Vortex overflow
Up Turbo Vortex sequence error
ICR read/merge FIFO overflow/underflow
TLMBPR FIFO overflow/underflow
Parity err on first cycle of up Turbo Vortex
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