Accessing Remote I/O Node Csrs Through Direct I/O Window Space; Sparse Address Space Reads - DEC AlphaServer 8200 Technical Manual

must not overwrite a mailbox that is still in use (<DONE> not set by the
I/O port).
The I/O system architecture requires that there be only a single software-
visible mailbox pointer CSR (TLMBPR) address. Once the software has
built a mailbox structure in main memory, it loads the I/O port's TLMBPR
register with the double hexword aligned address of the mailbox.
There are eight TLMBPR registers in the I/O port supporting four CPU
chips. A CPU node inserts the least significant bits of its virtual ID into
TLSB_BANK_NUM<1:0> during a CSR write to the TLMBPR register so
the I/O port can determine which two of the eight TLMBPR registers form
the pair that it should use. Table 6-2 shows the values inserted in
TLSB_BANK_NUM<1:0> by the CPUs. This allows a single CPU to have
up to two mailboxes pending within the I/O port at any given time. If
there are four or less CPU chips in the system, each CPU chip can have its
own pair of dedicated TLMBPR registers. Additional CPUs have to share
a TLMBPR register pair.
Table 6-2 TLMBPR Register Map
Mailbox pointers are managed by the I/O port hardware. If one or more
CPUs write the TLMBPR register such that two mailbox transactions are
pending for the same CPU virtual ID, additional CSR write transactions to
the TLMBPR register using the same virtual ID result in the TLSB write
transaction not receiving acknowledgment (TLSB_CMD_ACK not as-
serted). Processors use the lack of TLSB_CMD_ACK assertion on writes to
the mailbox pointer CSR to indicate a busy status. The write must be reis-
sued at a later point in time (through software).
The I/O port transmits the mailbox packets to the Down Hoses as though
all the TLMBPR registers constituted an eight-deep FIFO.

6.4.2 Accessing Remote I/O Node CSRs Through Direct I/O Window Space

There are two types of direct I/O window space structures: sparse address
space and dense address space.
NOTE: The TLSB address protocol is slightly different for sparse address space
reads and sparse address space writes. Therefore, these transactions are
described under separate subsections.
6.4.2.1

Sparse Address Space Reads

Figure 6-3 illustrates the TLSB address bus protocol for sparse address
space reads. Table 6-3 describes the sparse address space read protocol.
TLSB_BANK_NUM<1:0>
00
01
10
11
CPU Virtual ID TLMBPR Register Pair
0, 4, 8, or C TLMBPR0
1, 5, 9, or D TLMBPR1
2, 6, A, or E TLMBPR2
3, 7, B, or F TLMBPR3
I/O Port 6-15