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MCR—Memory Configuration Register
Address
BB + 0000 1880; BSB + 0000 1880
Access
R/W
The MCR register provides information about the DRAM array
structure including DRAM type and number of strings installed. It
includes a battery OK indication and battery disable when used
with the SRAM option. This information is required by the console
to set up the eight address mapping registers in each TLSB com-
mander node and the MIR register located on each memory mod-
ule. The MCR register also contains a 2-bit field (DTR) that is used
to select one of three cycle time variants.
A unique feature of this register is that it responds to a TLSB
broadcast space address (BSB+1880). This feature allows all mem-
ory modules to set the DRAM timing rate at the same time. This
feature is important to ensure that all memory modules continue
to refresh at the same time whenever MCR<DTR> is updated.
31 30 29 28 27
RSVD
BDC
BREN
BDIS
BAT
6
10
7
9
8
OPTION
SHRD
RSVD
DEFAULT
STRN
RSVD
DTYP
5
4
3
2
1
0
DTR
BXB-0769-93
System Registers 7-89
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