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7.4 CPU Module Registers
CPU module registers are divided into four groups:
The first three groups of registers are implemented in TLSB node space for
visibility. Gbus registers reside in the node private space.
NOTE: Accesses by a CPU to its own Gbus registers are treated as private accesses
and are performed through the TLPRIVATE location in broadcast space
(BSB + 0000).
Module-specific registers support module diagnostics, console operations.
or module functions that are CPU independent. CPU0 and CPU1 specific
registers are identical registers dedicated to a particular CPU. These reg-
isters provide the interrupt masking, identification, and communications
for each CPU. Gbus registers implement console/diagnostic/interrupt re-
lated functions. Table 7-20 lists the CPU module registers. Table 7-21
lists the Gbus registers.
Refer to Table 7-2 for the TLSB required registers implemented on the
CPU module.
7-44 System Registers
• Module-specific registers
• CPU0-specific registers
• CPU1-specific registers
• Gbus registers
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