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hose). The I/O port, however, could post up to five interrupts to the CPUs
at IPL 17 (one per hose plus one I/O port generated error interrupt).
When a CPU reads a specific TLILIDx register that contains a valid vector,
the I/O port builds an interrupt status return packet and returns it on the
appropriate Down Hose to the I/O adapter module. The one exception to
this rule is an I/O port internally generated error interrupt for which no
interrupt status return packet is required.
When a CPU reads a specific TLILIDx register that does not contain a
valid vector, the I/O port returns zero to the CPU and takes no further ac-
tion.
The I/O port drives TLSB_HOLD to handle interrupt status return buffer
overflows and certain error conditions. TLSB_HOLD is asserted to stall
the data bus transaction (for example, when a CPU does not yet know the
shared and dirty state of a block in its cache).
The TLSB_HOLD signal is asserted for one cycle and deasserted for one
cycle. This two-cycle sequence can be repeated until the device is ready to
proceed with the data transaction. Devices must disregard the value of
TLSB_HOLD received during the second cycle of each two-cycle sequence,
as it is Unpredictable. An assertion of TLSB_HOLD is converted inter-
nally to look like a two-cycle assertion.
Shared and Dirty are valid in the No_Hold cycle, which is the cycle where
Hold could not be asserted, but the bus is not held by any device. Data is
driven three cycles later (assuming TLSB_HOLD is not reasserted).
6.5.1.3
CSR Transactions
CPUs can access the I/O port's internal registers through CSR read and
write transactions. The I/O port's responder logic uses the transaction ad-
dress to select the appropriate register. The TLSB command determines
whether data is written into the selected register or the register's contents
are queued for return to the CPU that made the request.
A special class of transactions is initiated when the CPU issues a CSR
write command with the I/O port's Mailbox Pointer Register (TLMBPR) as
the destination. This operation initiates a mailbox transaction with an I/O
device on the XMI bus or the Futurebus+. I/O window space transactions
with a device on the PCI bus are initiated by TLSB CSR reads and writes
to I/O window space.
Mailbox Transactions
When a CPU successfully writes to the I/O port's TLMBPR register using a
write CSR command, the I/O port begins a mailbox transaction. The first
32 bytes of data are written by the CPU to inform the I/O port which I/O
bus is to be the recipient of the mailbox command, and to tell the remote
bus adapter what transaction is to be performed and what the write data
is, if any. The second 32 bytes of data are reserved for the completion
status of the mailbox transaction. Read data, if any, is deposited back into
memory, as are an error indication, a "done" flag, and device dependent
completion codes. The I/O port serves as an intermediary and forwards
the request to the target I/O bus.
The I/O port implements the mailbox pointer as a set of eight registers,
two per CPU. The registers that comprise the mailbox pointer are serviced
6-28 I/O Port
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