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TLEPMERR—MMG Error Register
Address
BB + 1580
Access
R/W
The TLEPMERR register contains CPU module error bits. These
bits are set as a result of errors detected in the MMG. This regis-
ter also contains the node reset status bit.
31
RSVD
D2DCPE3: DIGA to DIGA CSR Parity Error #3
D2DCPE2: DIGA to DIGA CSR Parity Error #2
D2DCPE1: DIGA to DIGA CSR Parity Error #1
D2MCPE: DIGA to MMG CSR Parity Error
A2MAPE1: ADG to MMG Address Parity Error #1
A2MAPE0: ADG to MMG Address Parity Error #0
4
3
2
8
7
5
6
RSTSTAT
BXB-0502-93
System Registers 7-59
1
0
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