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Check bits are computed by XORing all data bits corresponding to columns
containing a one in the upper table and inverting bits <3:2>. These check
bits are transmitted on the TLSB_ECC lines.
An error syndrome is computed by XORing all data and check bits corre-
sponding to columns containing a one in both tables and inverting bits
<3:2>. A syndrome equal to zero means no error. A syndrome equal to one
of the hex syndromes in the tables indicates the data or check bit in error.
Any other syndrome value indicates multiple bits in error and is
uncorrectable.
2.2.8.7
ECC Error Handling
Single-bit errors are detected by the transmitter and all receivers of data
and result in setting an error bit in the TLBER register. <CWDE> sets
during memory write commands, and <CRDE> sets during memory read
commands. The TLSB_DATA_ERROR signal is also asserted, informing
all nodes that an error has been detected. The node that transmitted the
data sets <DTDE> in its TLBER register so the transmitter can be identi-
fied. All participating nodes preserve the command code, bank number,
and syndrome. The memory node preserves the address.
Memory nodes do not correct single-bit errors. So it is possible for data
containing single-bit errors to be written to the bus. The source of the er-
ror can be determined by checking the nodes that detected the error, the
type of command, and the node type that transmitted the data.
Double-bit errors and some multiple-bit data errors are detected by the
transmitter and all receivers of data, and result in setting <UDE> in the
TLBER register. Double-bit errors are not correctable.
Some nodes are not able to correct single-bit errors in CSR data transfers.
If such a node receives CSR data with a single-bit error, it sets <UDE> in
its TLBER register.
2.2.8.8
TLSB_DATA_VALID
The TLSB_DATA_VALID<3:0> signals are additional data values trans-
mitted with data in each data cycle. The use of these signals is implemen-
tation specific.
2.2.8.9
TLSB_SHARED
The TLSB_SHARED signal is used by CPU nodes to indicate that the
block being accessed has significance to the CPU. It must be asserted if
the block is valid and is to remain valid in a CPU's cache. A CPU does not
drive TLSB_SHARED in response to commands it initiates.
TLSB_SHARED is asserted two cycles after TLSB_SEND_DATA. If any
node asserts TLSB_HOLD at this time, TLSB_SHARED is asserted again
two cycles later.
Note that multiple nodes can drive the TLSB_SHARED wire at one time.
All nodes must assert the signal in the same cycle and deassert it in the
following cycle.
If the TLSB_SHARED state of the data is not available as a response to
TLSB_SEND_DATA, TLSB_HOLD must be asserted until the state is
available.
2-22 TLSB Bus
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