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6.3.2.2
CSR Read Transactions to I/O Window Space
A CSR read command to node 4 through 8 I/O window space causes an I/O
port installed in that node to assemble a window read command packet
(sparse or dense, depending on the type of transaction) and transmit it on
the Down Hose. The I/O port returns Unpredictable data to the TLSB
commander node.
As soon as the I/O port empties the window read command packet from its
internal buffer, it issues a CSR write command to the Window Space Dec-
rement Queue Counter Register (TLWSDQRn) in CSR broadcast space.
The I/O port does not ACK the write broadcast transaction nor does it gen-
erate the associated data cycles. The I/O port then transmits a window
read command packet on the Down Hose and decrements its remote
adapter node buffer counters.
When the I/O port receives an error-free window Read Data Return packet
(sparse or dense, depending on the type of transaction) on the Up Hose, it
issues a CSR write command to the CSR Read Return Data register in
CSR broadcast space. During this transaction it asserts the VID of the
commander node onto the TLSB_BANK_NUM<3:0> field and returns the
read data on the first data cycle of the CSR write to broadcast space. It
also decrements the appropriate remote adapter node buffer counter.
If the window Read Data Return packet is in error, the I/O port issues a
CSR write command to the CSR Read Return Error register in broadcast
space. During this transaction it asserts the VID of the commander node
onto the TLSB_BANK_NUM<3:0> field and returns Unpredictable data on
the first data cycle of the CSR write to broadcast space.
If the read transaction fails to complete after n seconds, the CPU aborts
the transaction.
The CPUs keep track of the number of outstanding CSR transactions is-
sued and guarantee that no more than four uncompleted CSR transactions
to a single I/O port node are pending at a given time. A transaction is con-
sidered complete only after the I/O port has issued its corresponding CSR
write to the WSDQRn register in broadcast space.
In addition, a single CPU may not have more than one outstanding CSR
read transaction pending at a given time.
6.3.3 Interrupt Transactions
The I/O port generates two types of interrupts on the TLSB:
6.3.3.1
Remote Bus Interrupts
When an I/O interrupt is posted to a CPU, the CPU reads the vector from
the appropriate I/O port. This means that the INTR/IDENT packet gener-
ated by an I/O adapter module must already contain the vector so that the
I/O port can load it into one of its Interrupt Levelx IDENT registers (TLI-
LIDx) and have it ready to return to the CPU.
6-8 I/O Port
• Remote bus interrupts, which originate from a remote node and are
received by the I/O port on the Up Hose
• I/O port generated error interrupts, which originate within the I/O port
as a result of an internally detected error condition
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