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It should also be noted that, due to the extra I/O port generated error in-
terrupt, as many as five interrupts could be pending on IPL 17 at any
given time, one I/O port generated error interrupt and four remote node in-
terrupts received by the I/O port from the Up Hose.
6.3.4 DMA Read Transactions
I/O modules transfer large blocks of data directly to and from memory us-
ing DMA transactions. When an I/O device requests its local I/O bus for a
DMA read transaction, the I/O bus adapter acknowledges the read transac-
tion and, if the bus supports it, pends the transaction. This frees the I/O
bus for other bus traffic. The I/O bus adapter then transmits a DMA read
request packet to the I/O port on the Up Hose. Included in the DMA read
request packet is the target TLSB address, a tag field to allow the I/O bus
adapter to associate the DMA read request with the DMA return data
packet, and the length code indicating the amount of data requested.
Upon receiving the DMA read request packet, the I/O port generates a
TLSB system bus read transaction. If the read is successful, the I/O port
transmits a DMA read data return packet to the I/O bus adapter on the
Down Hose. The DMA read data return packet includes the tag from the
corresponding DMA read request packet, the length code, an error bit indi-
cating whether or not the DMA read request was successful, and the re-
quested data. The I/O bus adapter then transmits the data across the I/O
bus to the appropriate I/O device.
If the read is unsuccessful, the I/O port generates an error interrupt and
transmits a DMA read data return packet with the error bit set to the I/O
bus adapter over the Down Hose. The I/O bus adapter then takes the ap-
propriate action on the I/O bus for read errors.
6.3.5 DMA Interlock Read Transactions
The TLSB memory system does not support XMI style hardware memory
locks; that is, no IREAD/UWMASK instruction pair equivalence exists on
the TLSB. VAX CI-port architecture devices, however, require this type of
hardware memory lock. Therefore, to support these devices on the TLSB
platform, the I/O port utilizes TLSB memory bank lock commands to ac-
complish an atomic memory Read-Modify-Write function that closely re-
sembles an IREAD instruction. This function is implemented only for XMI-
based nodes.
VAX CI-port architecture devices acquire hardware memory locks using
DMA IREAD transactions. All DMA IREAD transactions are quadword in
length and quadword-aligned. When an I/O device on the XMI issues a
6-10 I/O Port
• I/O port generated error interrupts transmit a special vector on the
TLSB, which must be preloaded by system software into the I/O port
Interrupt Vector Register (TIVR) at system initialization.
• The I/O port has a special I/O port interrupt mask bit, <INTR_NSES>,
that must be loaded by software at system initialization.
<INTR_NSES> causes all I/O port specific generated error interrupts
to be enabled/disabled (for example, TLSB ECC error, hose parity er-
ror, and so on).
• I/O port generated error interrupts do not return an interrupt status
packet to the Down Hose.
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