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Table 7-48 MDRA Register Bit Definitions (Continued)
Name
Bit(s)
<29:28>
RFR
<27:9>
RSVD
DEDA
<8>
<7>
POEMC
1 If <POEM> is set and an error occurs on Bank0 of two back-to-back reads in modules of greater than one string, an
error detected on the second read to Bank1 will not be reported.
2 When an error is detected during POEM mode, the data bit(s) in error will be logged in the STDERA,B,C,D,E regis-
ters in each MDI ASIC. Since the assertion of POEMC will not clear the error bits in the STDERA:E registers, it is
required that the user set bit <1> in DDR0:3 prior to setting <POEMC>.
Type
Function
R/W, 01
Refresh Rate. Determines the refresh rate of
the module.
<RFR>
00
01
10
11
R0
Reserved. Read as zero.
R/W, 01
TLSB_DATA_ERROR Disable. When set and
used in conjunction with POEM or FRUN modes,
TLSB_DATA_ERROR will not assert if an error
is detected. This bit would be set by a user that
wishes to run POEM or FRUN self-test modes in
a system environment (console mode) where the
assertion of TLSB_DATA_ERROR would prevent
the system from operating correctly.
W, 0
Pause on Error Mode Continue. When set in
conjunction with <POEM> and <EXST> of this
register, causes memory self-test to continue exe-
cuting from the point where it halted due to an
error condition being detected. At this point self-
test will either halt on the next error, or con-
tinue to loop. <EXST> is cleared by software,
when TLSB_RESET is asserted or <NRST> is
set. When asserted following an error detection,
the STER and STAIR registers are cleared. This
bit is only valid when self-test is in POEM mode.
Setting this bit during other self-test modes re-
sults in Undefined operation.
Refresh Rate
1X
2X (Default)
4X
Reserved
1,2
System Registers 7-99
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