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drive the address and command, the outcome of the tag lookup can be
evaluated by the bus interface. If the lookup is a hit, then the CPU bus
interface nulls the TLSB command field and cancels the request. Although
this consumes potentially needed address bus slots, the address bus re-
quires two cycles to initiate a command and the data bus requires three cy-
cles per transaction. This means that there are surplus address bus slots
beyond the number required to keep the data bus busy. Therefore, the
penalty of a false arbitration on data bus bandwidth is minimized. The
pipelined nature of the bus means that there are potential bank conflicts
that can only be resolved by nulling the address command. The bank de-
code can also be hidden under the request and arbitration cycles.
Bus arbitration by the CPU under these aggressive conditions is called
"early arbitration." When the request has to be nulled due to bank conflict
or a cache hit, it is called "false arbitration."
All address bus commands (except nulled commands) require acknowledg-
ment two cycles after the issue of the bank address on the bus, or no data
is transferred. This mechanism permits the commander node to determine
if a slave node will respond. On a normal transaction when a commander
issues a request, the sequencing of the data bus is the responsibility of the
slave node. All nodes must look for the acknowledgment; only acknowl-
edged commands sequence the data bus.
The address bus permits flow control by use of the signal TLSB_ARB_SUP.
This signal permits commander nodes to stop address bus arbitration, thus
preventing further addresses from propagating to the bus.
All TLSB memory transactions take place on a cache block boundary (64
bytes). Memory is accessed with signals TLSB_ADR<39:5> on the address
bus. TLSB_ADR<39:6> addresses one block. TLSB_ADR<5> specifies the
first 32-byte subblock to be returned (wrapped). Use of TLSB_ADR<4:3>
is implementation specific. Figure 2-1 shows mapping of physical ad-
dresses to the address bus.
Figure 2-1
TLSB Memory Address Bit Mapping
Two special address bus commands permit an I/O device to perform atomic
transactions on sizes under 64 bytes. The first command permits a 64-byte
read to put a special lock on a bank, and the second command permits the
subsequent write to unlock the bank. Because a busy bank cannot be ac-
cessed by another node, this command pair guarantees atomic access to
the cache block that needs to be modified.
3 9
Processor Byte Address
64-Byte Block Address
3 9
4
6
5
0
Wrap
Address
Bus
Field
6
5
BXB0828.AI
TLSB Bus 2-7
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