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6.8.2.2
Mailbox Transaction
All mailbox transactions are executed by the HPC as a PCI master.
Mailbox transactions forwarded from the HDR can access a PCI I/O device
through the PCI bus, an HPC CSR, or the map RAM. Mailbox transac-
tions to PCI memory or I/O space on the PCI bus are sent to both PCI
buses. However, only one bus responds to the transaction.
Mailbox transactions are byte, word, tribyte, longword, or quadword in
length. A Mailbox Command packet is received by the HPC on the Down
Hose. Each of the HPCs independently decodes the command, although
only one executes it. After executing the mailbox read or write command
to the appropiate destination, the executing HPC returns a mailbox status
packet to the HDR over the Up Hose. Data is included in the Up Hose
packet if the command was a mailbox read.
Mailbox transactions are used for diagnostics and initialization. Although
the HPC can buffer up to four mailbox transactions, it executes only one
transaction at a time. The HDR sends one mailbox transaction at a time
to the HPC.
6.8.2.3
CSR Transactions
All CSR transactions are executed by the HPC as a PCI master. CSR
transactions generated by the HDR can access a location on the PCI bus,
an HPC CSR, or the map RAM and flash ROM. CSR transactions to PCI
memory or I/O space on the PCI bus are sent to both PCI buses, with only
one bus actually responding to the transaction.
CSR transactions are byte, word, tribyte, longword, quadword, or hexword
in length. Byte, word, tribyte, longword, and quadword transfers are sup-
ported through a sparse CPU-to-PCI address mapping. Byte, word,
tribyte, and longword transfers result in a PCI length burst of one.
Quadword transfers result in a PCI burst length of two. Hexword trans-
fers result in a PCI length burst of eight.
Each HPC independently decodes the CSR command, although only one
HPC executes it. After executing the CSR read or write command to the
appropriate destination, the executing HPC returns a CSR status packet to
the HDR over the Up Hose. Data is included in the Up Hose packet if the
command was a CSR read.
The HPC can buffer up to four CSR transactions, thus reducing the wait
time between the end of one transaction on the PCI bus and the start of
the next transaction on the PCI bus.
Memory Channel writes received from the HDR are handled in the same
manner as CSR transactions.
6.8.2.4
Interrupt Transactions
Each HPC accepts the PCI device interrupts from the bus it interfaces to.
Each HPC contains 17 interrupt vector registers that are programmable by
software. Sixteen of the registers hold hardware device interrupt vectors,
and one register holds an error interrupt vector.
The interrupts are latched and prioritized in the HPC. The HPC generates
an INTR/IDENT by accessing the CSR that contains the selected inter-
6-84 I/O Port
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