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Hose PWROK Transitioned and Hose Error are technically hose errors,
not internal I/O port errors. However, they are handled by the I/O port in
the same manner as internal errors.
The posting of IPL 17 error interrupts are enabled by software by setting
ICCNSE<INTR_NSES> after a unique interrupt vector for the I/O port
has been loaded into the IDR Vector Register. Once enabled, the I/O port
posts an IPL 17 interrupt when one of the above error conditions is de-
tected. However, the I/O port does not issue any further IPL 17 error inter-
rupts until all the error bits listed above are clear.
It is important to note that reads to the TLILID3 register return the vector
from the the IDPVR register ahead of any posted IPL 17 device interrupts
vectors, regardless of the order in which the interrupts were posted.
6.7.7 Address Bus Errors
The TLSB address bus uses parity protection across the command, bank
number, and address fields. Additionally, all drivers on the TLSB check
the data received from the bus against the expected data driven on the
bus. This combination of parity and transmit/receive checking ensures a
high level of error detection.
6.7.7.1
TLSB Address Transmit Check Errors
The I/O port checks that its TLSB bus assertions get onto the bus properly
by receiving a signal back from the bus and comparing it to what was
driven. A mismatch can occur because of a hardware error on the bus, or
if two nodes attempt to drive the fields in the same cycle. If a mismatch
occurs, the I/O port sets a bit in the TLBER register and asserts
TLSB_FAULT.
The I/O port supports two types of transmit checks:
The I/O port level checks the following address bus fields when it has won
the bus and has driven a command/address cycle. If the I/O port detects a
mismatch, it sets <ATCE> and asserts TLSB_FAULT.
The I/O port level checks the request signals (as determined from
TLSB_NID<2:0>) every bus cycle. If it detects a mismatch, it sets <RTCE>
and asserts TLSB_FAULT.
6-70 I/O Port
• Level Transmit Checks are used when signals are driven by a single
node in specific cycles. The assertion or deassertion of each signal is
compared to the level driven. Any signal not matching the level driven
is in error.
• Assertion Transmit Checks are used on signals that may be driven by
multiple nodes or when the assertion of a signal is used to determine
timing. An error is declared only when a node receives a deasserted
value, and an asserted value was driven. These checks are performed
whenever the I/O port is driving the signal with the asserted value.
• TLSB_ADR<39:5>
• TLSB_ADR_PAR<1:0>
• TLSB_CMD<2:0>
• TLSB_BANK_NUM<3:0>
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