Tlesrn-Error Syndrome Registers; Tlesrn Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

TLESRn—Error Syndrome Registers
Address BB + 0680 through 0740
Access R/W
The TLESRn registers contain the status information on a data er-
ror within a 64-bit slice of the data.
TLESR0 contains the error syndrome and status derived from
TLSB_D<63:0>, TLSB_ECC<7:0>, and TLSB_DATA_VALID<0>.
TLESR1 contains the error syndrome and status derived from
TLSB_D<127:64>, TLSB_ECC<15:8>, and TLSB_DATA_VALID<1>.
TLESR2 contains the error syndrome and status derived from
TLSB_D<191:128>, TLSB_ECC<23:16>, and TLSB_DATA_VALID<2>.
TLESR3 contains the error syndrome and status derived from
TLSB_D<255:192>, TLSB_ECC<31:24>, and TLSB_DATA_VALID<3>.
31 30
RSVD
LOFSYN
CRECC: Correctable
Read ECC Error
CWECC: Correctable
Write ECC Error
Table 7-11 TLESRn Register Bit Definitions
Name Bit(s)
<31>
LOFSYN
<30:24>
RSVD
7-26 System Registers
23 22 21 20 19 18 17 16 15
24
CPU1
CPU0
Type Function
R/W, 0 Lock on First Syndrome. When set, the TLESR
register locks on the first error.
R/W, 0 Reserved. Must be written as zero.
8 7
SYND1
TDE: Transmitter During Error
TCE: Transmitter Check Error
CPU and I/O: DVTCE; MEM: RSVD
UECC: Uncorrectable ECC Error
0
SYND0
BXB-0784C-94