DEC AlphaServer 8200 Technical Manual page 6

Chapter 4 Memory Subsystem
4.1 Internal Cache ............................................................................................................... 4-1
4.1.1 Instruction Cache ................................................................................................... 4-1
4.1.2 Data Cache .............................................................................................................. 4-1
4.1.3 Second-Level Cache ................................................................................................ 4-2
4.2 Backup Cache ................................................................................................................ 4-2
4.2.1 Cache Coherency .................................................................................................... 4-2
4.2.2 B-Cache Tags .......................................................................................................... 4-3
4.2.3 Updates and Invalidates ........................................................................................ 4-4
4.2.4 Duplicate Tags ........................................................................................................ 4-4
4.2.5 B-Cache States ........................................................................................................ 4-4
4.2.6 B-Cache State Changes ......................................................................................... 4-5
4.2.7 Victim Buffers ......................................................................................................... 4-6
4.2.8 Lock Registers ......................................................................................................... 4-6
4.2.9 Cache Coherency on Processor Writes .................................................................. 4-8
4.2.10 Memory Barriers .................................................................................................... 4-9
4.3 Main Memory ................................................................................................................ 4-9
4.3.1 Major Sections ...................................................................................................... 4-10
4.3.1.1 Control Address Interface ............................................................................. 4-11
4.3.1.2 Memory Data Interface ................................................................................. 4-11
4.3.1.3 DRAM Arrays ................................................................................................. 4-12
4.3.2 Memory Organization .......................................................................................... 4-13
4.3.3 Refresh .................................................................................................................. 4-16
4.3.4 Transactions ......................................................................................................... 4-16
4.3.5 ECC Protection ....................................................................................................... 2-2
4.3.6 Self-Test ................................................................................................................ 4-16
4.3.6.1 Self-Test Modes .............................................................................................. 4-17
4.3.6.2 Self-Test Error Reporting .............................................................................. 4-18
4.3.6.3 Self-Test Operation ........................................................................................ 4-18
4.3.6.4 Self-Test Performance .................................................................................... 4-19
Chapter 5 Memory Interface
5.1 Control Address Interface ............................................................................................. 5-1
5.1.1 TLSB Control .......................................................................................................... 5-1
5.1.1.1 Memory Bank State Machine ........................................................................ 2-11
5.1.1.2 CSR State Machine ........................................................................................ 2-12
5.1.1.3 TLSB Input Latches ......................................................................................... 2-5
5.1.1.4 TLSB Bus Monitor ........................................................................................... 2-6
5.1.1.5 TLSB Command Decode .................................................................................. 2-6
5.1.1.6 TLSB Bank Match Logic .................................................................................. 2-8
5.1.1.7 TLSB Parity Check .......................................................................................... 2-8
5.1.1.8 TLSB Sequence Control ................................................................................... 2-9
5.1.1.9 TLSB Bank Available Flags .......................................................................... 2-11
5.1.2 DRAM Control ...................................................................................................... 2-12
5.1.3 Address/RAS Decode Logic .................................................................................. 2-12
5.1.3.1 128MB/512MB Memory Module Addressing ................................................ 2-12
5.1.3.2 256MB/1024MB Memory Module Addressing .............................................. 2-13
5.1.3.3 512MB/2048MB Memory Module Addressing .............................................. 2-13
5.2 Memory Data Interface ................................................................................................. 5-9
5.2.1 Data Path Logic .................................................................................................... 2-14
5.2.2 Write Data Input Logic ........................................................................................ 2-14
5.2.2.1 Write Data Buffer ............................................................................................ 5-9
5.2.2.2 Write Data Path ECC Algorithm .................................................................. 2-15
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