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If one CPU drives TLSB_HOLD while another drives TLSB_SHARED or
TLSB_DIRTY, the second keeps driving TLSB_SHARED and
TLSB_DIRTY. TLSB_HOLD, TLSB_SHARED, and TLSB_DIRTY are as-
serted for one cycle and deasserted in the next cycle. This two-cycle se-
quence repeats until TLSB_HOLD is not reasserted (the no-Hold cycle).
Receivers internally convert TLSB_HOLD to appear asserted in both cy-
cles. The value received from the bus in the second cycle is Unpredictable.
Three cycles after the no-Hold cycle data is driven on the bus.
Another slave device could drive its TLSB_SEND_DATA as TLSB_HOLD
is being asserted for the previous transaction. TLSB_SEND_DATA asser-
tions when TLSB_HOLD is asserted are ignored. The slave device must
keep driving TLSB_SEND_DATA.
2.2.8.2
Sequence Numbers
As TLSB_SEND_DATA is being driven, the slave device also drives
TLSB_SEQ<3:0> to indicate the sequence number of the request being
serviced. All commanders check the sequence number against the se-
quence number they expect next. A sequence number of zero is always ex-
pected with the first assertion of TLSB_SEND_DATA after a reset se-
quence. The sequence number increments in a wrapping 16 count manner
for each subsequent assertion of TLSB_SEND_DATA.
2.2.8.3
Sequence Number Errors
If the sequence numbers of data bus transactions do not match the ex-
pected sequence number, then an out-of-sequence-fault has occurred.
<SEQE> sets in the TLBER register. This is a system fatal error. All out-
standing requests are aborted and the system attempts to crash.
2.2.8.4
Data Field
The data field (data bus) is 256 bits wide. A 64-byte block is returned from
memory in two bus cycles. A third cycle is added during which no data is
driven to allow the bus to return to an idle state.
2.2.8.5
Data Wrapping
Data wrapping is supported for memory access commands. The address
driven during the command/address cycle represents bits <39:5> of the 40-
bit physical byte address. Address bits <4:3> appear on the bus but are
ignored. TLSB_ADR<39:6> uniquely specify the 64-byte cache block to be
transferred. TLSB_ADR<5> specifies the 32-byte wrapping as shown in
Table 2-5. Data cycle 0 refers to the first transfer; data cycle 1 to the sec-
ond. TLSB_ADR<5> is valid for all memory access transactions; both
reads and writes are wrapped.
2-20 TLSB Bus
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