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5.3.2.4
CSRCA Parity
The CSRCA bus is protected by byte-wide odd parity. All data transmitted
over this bus is accompanied by a valid parity bit (CSRCA<8>) to be
checked against the data by all chips. Parity errors on the CSRCA bus
during CSR read transactions cause Unpredictable data to be returned to
the TLSB bus. Receiving data with bad ECC from the TLSB on CSR write
transactions causes the CSRCA parity bit to be inverted, forcing bad par-
ity. Any parity error that occurs on the CSRCA bus during a write dis-
ables that particular data byte from being written. Note that other data
bytes of the same register may have already been written.
5-18 Memory Interface
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