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Table 7-30 TLEPDERR Register Bit Definitions
Name
RSVD
Ctrl/P_HALT_ENA
HALT_ENA
INTIM_ENA
IP_ENA
IPL17_ENA
IPL16_ENA
IPL15_ENA
IPL14_ENA
DUART0_ENA
7-64 System Registers
Bit(s)
Type
Function
<31:9>
R/W, 0
Reserved. Must be written as zeros.
<8>
R/W, 0
Ctrl/P Halt Enable. Enables halt through ^P if
<TLSB_SECURE> of GBUS$MISCR is not set,
and if a ^P Halt interrupt is received from the
Gbus.
<7>
R/W, 0
CPU Halt Enable. Enables halts by writes to
TLCNR<HALT> for this CPU.
<6>
R/W, 0
Interval Timer Interrupt Enable. The inter-
val timer can be set to interrupt or to be polled. If
the timer is set to interrupt, the interrupts can be
directed to either CPU or to both.
<5>
R/W, 0
Interprocessor Interrupt Enable. When set,
enables interprocessor interrupts to this register's
associated CPU.
<4>
R/W, 0
IPL17 Interrupt Enable. If set, IPL17 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register's associated CPU.
<3>
R/W, 0
IPL16 Interrupt Enable. If set, IPL16 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register's associated CPU.
<2>
R/W, 0
IPL15 Interrupt Enable. If set, IPL15 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register's associated CPU.
<1>
R/W, 0
IPL14 Interrupt Enable. If set, IPL14 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register's associated CPU.
<0>
R/W, 0
DUART0 Interrupt Enable. If set, enables
DUART interrupts from DUART0 to this regis-
ter's associated CPU.
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