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6.6 Hose Interface
The I/O port communicates with the I/O bus adapters over dual-cable
buses. These buses are called hoses. The I/O subsystem architecture sup-
ports four separate I/O bus adapters, as shown in Figure 6-1.
Each hose consists of two separate unidirectional interconnects: a Down
Hose, which transmits command/address and data from the I/O port to the
I/O bus adapter module; and an Up Hose, which transmits command/ad-
dress and data from the I/O bus adapter module to the I/O port.
Both the Up Hose and the Down Hose use clock forwarding. That is, the
clock is transmitted on the hose at the data source end and is used to
strobe the data into a receiving register at the receiving end.
The Down Hose implements a 32-bit parity protected data bus. The Up
Hose implements a 36-bit parity protected data/control bus.
The I/O port supports three types of I/O bus adapter modules:
The I/O port derives the Down Hose clock from the Up Hose clock. Thus,
both the Down Hose clock and the Up Hose clock run at the same fre-
quency (although they are asynchronously skewed).
6.6.1 Hose Protocol
The I/O port and the I/O bus adapter map transactions on their respective
buses into hose protocol packets. The protocol includes operations for
mailbox I/O, window I/O (direct CSR access), device interrupts, and DMA.
Five packet types are transmitted on the Down Hose:
Mailbox Command packets are generated as a result of a CPU action. The
I/O port must assure that only one Mailbox Command packet is issued on
the Down Hose at a time. The I/O port must receive a Mailbox Status Re-
turn packet on the Up Hose before it will issue another Mailbox Command
packet. Therefore, as long as the I/O adapter reserves space in its Down
Hose FIFO to store at least one Mailbox Command packet, its Down Hose
mailbox FIFO will never overflow.
Window Read/Write Command packets result from CPU accesses. The I/O
bus adapter informs the I/O port of the number of outstanding Window
Read/Write Command packets it can accept without overflowing (up to 15).
This limit (that is, the total number of buffers) is passed in each window-
related Up Hose packet. The I/O port maintains a counter for each hose.
Each time the I/O port transmits a Window Read/Write Command packet
on the Down Hose, it increments that hose's counter. Each time the I/O
• XMI adapter (DWLMA) module – 32 ns clock cycle time
• Futurebus+ adapter (DWLAA) module – 25 ns clock cycle time
• PCI bus adapter (DWLPA) module – 30 ns clock cycle time
• Mailbox Command packets
• Window Read/Write Command packets
• DMA Read Data Return packets
• INTR/IDENT Status Return packets
• Memory Channel Write packets
I/O Port 6-35
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