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Glossary
ADG
Address gate array.
Bank
Smallest group of DRAMs that can be interleaved. A bank consists of one
or more strings.
Block
64 bytes of data within naturally aligned boundaries.
CTL
Control address interface.
DDB
DRAM data bus. The 576-bit bidirectional data bus that interfaces be-
tween the DRAM chips and the MDC gate arrays.
DIGA
Data interface gate array.
Direct mapped I/O access
A method of accessing I/O space on certain I/O bus adapters such as the
integrated I/O section and the DWLPA. Window space access is direct
mapped.
Down HDR
Hose to data path chip that transmits transactions to the Down Hose.
Down Hose
The cable that transmits data and control information from the I/O port to
an I/O bus adapter module.
External Hose
The connection (hose cable) between the I/O port and a single I/O bus
adapter module.
FBUS+
Futurebus+.
Glossary-1
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