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Table 7-52 DDRn Register Bit Definitions (Continued)
Name
Bit(s)
<2>
ICFR
<1>
CDER
<0>
LOE
7-108 System Registers
Type
Function
R/W, 0
Inhibit Clear on Free Run. When set in con-
junction with MDRA<FRUN>, the contents of
the STDER registers accumulate errors detected
by self-test. When ICFR is cleared, the contents
of the STDER registers will be cleared when self-
test reenters the start execution phase due to
<FRUN> set. This bit is valid only when self-
test is in free run mode. If set during other self-
test modes, operation is Undefined.
W, 0
Clear Self-Test Data Error Registers. When
set, clears the Self-Test Data Error Registers
(STDERA:E). This bit is normally used in con-
junction with MDRA<POEM>. When <POEM>
is set and an error is detected, self-test will halt
and lock the error bit(s) in the STDERx_n regis-
ters. This function is normally exercised after
an error halt, prior to continuing self-test
(through <POEMC>) when in pause on error
mode. Failure to set this bit following a POEM
halt results in the STDERx_n registers accumu-
lating data bit errors.
R/W, 0
Lock on Error. When set, the contents of the
STDERn registers and the contents of the STER
registers lock and save the failing data bit(s),
failing string, and which MDI(s) detected the er-
ror upon the first detection of an error during
pause on error mode self-test operation. If this
bit is set during other self-test modes, operation
is Undefined.
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