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Table 7-4 TLBER Register Bit Definitions (Continued)
Name
Bit(s)
<2>
BAE
<1>
APE
7-12 System Registers
Type
Function
W1C, 0
Bank Available Violation Error. Set when a
memory bank is addressed by a memory access
command while the memory bank is busy. Also
set when any node detects a CSR access com-
mand while a CSR command is already in pro-
gress. This is a system fatal error that asserts
TLSB_FAULT.
I/O: Also sets <ADTE>.
W1C, 0
Address Parity Error.
CPU: Set when a node detects even parity on
the TLSB_ADR<30:5> and TLSB_ADR_PAR sig-
nals, or on the TLSB_ADR<39:31>,
TLSB_ADR<4:3>, TLSB_BANK_NUM<3:0>,
TLSB_CMD<2:0>, and TLSB_CMD_PAR sig-
nals. This is a system fatal error that asserts
TLSB_FAULT. When this bit is set, <ATDE> is
also set.
Memory: Set when a node detects even parity on
the TLSB_ADR<30:5> and TLSB_ADR_PAR sig-
nals, or on the TLSB_ADR<39:31>,
TLSB_ADR<4:3>, TLSB_BANK_NUM<3:0>,
TLSB_CMD<2:0>, and TLSB_CMD_PAR sig-
nals. This is a system fatal error that asserts
TLSB_FAULT. When this bit is set, <ATDE> is
also set.
I/O: Set when I/O port detects even parity on
the TLSB_ADR<30:5> and TLSB_ADR_PAR<0>
signals, or on the TLSB_ADR<39:31>,
TLSB_BANK_NUM<3:0>, TLSB_CMD<2:0>,
and TLSB_CMD_PAR<1> signals. This is a sys-
tem fatal error that asserts TLSB_FAULT.
When this bit is set, <ATDE> is also set.
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