Write Csr (Interrupt) Data Format - DEC AlphaServer 8200 Technical Manual

and so on. Figure 6-10 shows the format of the data used by the I/O port in
the CSR write (interrupt) transaction.
Figure 6-10

Write CSR (Interrupt) Data Format

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Only one CSR transaction may be active at a time. Note that there is no
TLSB_BANK_AVL signal for CSRs, as it is implied and does not appear on
the TLSB bus.
CPUs monitor CSR write transactions to the TLIOINTRx to detect when
they have been targeted by an interrupt. The I/O port may send up to 4
interrupts at IPL 14-16 (one per hose) and 5 interrupts at IPL 17 (one from
each hose and one for I/O port internal errors) to a given CPU. These in-
terrupts, at the same IPL for one CPU, would occur over separate writes
to the TLIOINTR register. When the CPU is ready to service the inter-
rupt, it performs a CSR read of the TLILIDx register in the I/O port. The
I/O port returns the contents of the appropriate TLILIDx register.
NOTE: The "x" in TLILIDx corresponds to the register number that serves a given
interrupt priority level (IPL). TLILID0 holds the IDENT vectors for IPL 14
interrupts, TLILID1 holds the IDENT vectors for IPL 15 interrupts, and so
forth.
The hose ID can be included in bits <14:15> of the interrupt vector if de-
sired. This optional mode of operation is enabled by setting bit <4> of the
IDPMSR register to one.
From the I/O port's perspective, there are two classes of interrupts. The
first class consists of interrupts generated by devices external to the I/O
port, that is through I/O devices on the XMI bus, Futurebus+, or PCI bus.
The second class consists of interrupts generated by the I/O port itself. In-
terrupts of the latter class serve to indicate error conditions detected by
the I/O port.
The TLILID0, TLILID1, and TLILID2 registers are each a queue of four
possible pending interrupts at IPL 14, IPL 15, and IPL 16, respectively
(one interrupt per hose per IPL). The vectors are returned to the CPUs in
the order in which the interrupts have arrived. The TLILID3 register
queue is five deep, one IPL 17 interrupt per hose plus one internally gener-
ated I/O port IPL 17 error interrupt.
The I/O port generates a high-level interrupt (IPL 17) when it detects an
error condition. This interrupt may be either enabled or disabled by set-
ting or clearing ICCNSE<INTR_NSES>. The I/O port's interrupt is the
most important possible within the I/O system and therefore takes prece-
dence over other IPL 17 interrupts. This is implemented by having the I/O
port always return its IDENT vector first when a CPU reads the TLILID3
register, even though there may be IPL 17 pending interrupts.
It should be noted that at IPL 14, IPL 15, and IPL 16 the I/O port will
never post more than four interrupts to the CPUs at a given IPL (one per
IPL
RSVD
<17:14>
9 8 7 6 5 4 3 2 1 0
CPU Mask
BXB0814.AI
I/O Port 6-27