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Table 7-4 TLBER Register Bit Definitions (Continued)
Name
Bit(s)
<6>
ACKTCE
<5>
RTCE
<4>
NAE
<3>
LKTO
Type
Function
W1C, 0
Acknowledge Transmit Check Error. Set
when a transmit check error is detected on the
TLSB_CMD_ACK signal. This is a system fatal
error that asserts TLSB_FAULT.
I/O: Also sets <NAE> if I/O port was com-
mander of transaction.
W1C, 0
Request Transmit Check Error. Set when a
transmit check error is detected on a request sig-
nal: TLSB_REQ<7:0>, TLSB_REQ8_HIGH,
TLSB_REQ8_LOW. This is a system fatal error
that asserts TLSB_FAULT.
Memory: Not implemented.
W1C, 0
No Acknowledge Error. Set when a com-
mander fails to receive an expected
TLSB_CMD_ACK in response to a CSR com-
mand.
CPU: This is a fatal error when the CSR opera-
tion is a write to other than one of the TLMBPR
registers. In this case, <CSR_NXM_WR> in the
TLEPAERR register also sets. When the opera-
tion is a CSR read, bogus data is cycled back to
DECchip 21164 and FILL_ERROR is asserted to
the DECchip 21164.
Memory: Not implemented.
I/O: When set, I/O port posts an IPL 17 inter-
rupt if interrupts are enabled.
W1C, 0
Bank Lock Timeout. Set when a memory node
times out waiting for a Write Bank Unlock com-
mand after processing a Read Bank Lock com-
mand. This is a hard error. The memory node
asserts TLSB_BANK_AVL upon setting
<LKTO>. This error is disabled if LKTOD is set
in the TLCNR register.
CPU: Not used.
I/O: Not implemented.
System Registers 7-11
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