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Consequently, the priority of any device will eventually bubble up to the
highest level. The no-op command is the only non-data transfer command;
it does not affect priorities.
TLSB_REQ8_HIGH and TLSB_REQ8_LOW are assigned to the I/O mod-
ule in node 8. These lines represent the highest and the lowest arbitration
priorities. The I/O port uses the high-priority line to guarantee a worst-
case latency. I/O ports residing in any node other than node 8 do not have
a guaranteed latency and arbitrate in the same manner as CPU modules,
using the request line assigned to that node.
2.2.4.6
Address Bus Request
A module may request the bus during any cycle. The mechanism for
granting the bus is pipelined. The request cycle is followed by an arbitra-
tion cycle and then by a cycle where the command, address, and bank
number are driven on the bus. A new command and address can be driven
in every second cycle.
Idle, request, and arbitration cycles differ as follows. An idle cycle is one
in which no request line is asserted and no arbitration is taking place. A
request cycle is the first one in which a request is asserted, and every sec-
ond bus cycle after that in which a request is asserted until the bus re-
turns to an idle state. An arbitration cycle is defined as the cycle following
a request cycle.
A device requests the bus by asserting its request line. In the next cycle
all devices arbitrate to see which wins the bus. The winner drives its com-
mand type, address, and bank number onto the bus and deasserts the re-
quest. The targeted memory module responds by asserting TLSB_CMD_
ACK and by deasserting the TLSB_BANK_AVL line for the targeted bank.
When a module wins arbitration for the bus, whether for real arbitration
or as a result of a false arbitration, it deasserts its request line in the fol-
lowing cycle even if the module has another outstanding transaction.
2.2.4.7
Asserting Request
On a busy bus, every second cycle is considered a request cycle. Request
lines asserted in nonrequest cycles are not considered until the next re-
quest cycle (one bus cycle later). Request lines asserted in nonrequest cy-
cles do not get any priority over lines asserted in the request cycle.
When more than one device requests the bus simultaneously, the device
with the highest priority wins the bus. Note that a new address can be
driven only once every two bus cycles.
2.2.4.8
Early Arbitration
CPU modules on the TLSB are allowed to arbitrate for the bus in anticipa-
tion of requiring it. This mechanism is referred to as "early arbitration"
and is used to minimize memory latency. The bus protocol provides a
mechanism for a CPU to request the bus, win it, and subsequently issue a
no-op command. This mechanism is referred to as "false arbitration."
A device that implements early arbitration can assert its request line be-
fore it requires the bus. If it happens that the bus is not required, the de-
vice can deassert its request line at any time. If a request line is asserted
TLSB Bus 2-13
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