Tlmcr-Memory Control Register; Tlmcr Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

TLMCR—Memory Control Register
Address BSB + 1880
Access W
The TLMCR register is used by memory nodes to set DRAM timing
rates. DRAM timing is dependent on bus cycle time and must be
written into each memory node to ensure the most efficient mem-
ory operation. DRAM timing affects the memory's refresh rate. To
allow memory nodes to refresh simultaneously, this register sets
DRAM timing in all memory nodes in the system.
31
Table 7-19 TLMCR Register Bit Definitions
Name Bit(s)
<31:6>
RSVD
DTR <5:4>
RSVD <3:0>
RSVD
Type Function
W, 0 Reserved. Must be zero.
W, 0 DRAM Timing Rate. Contents of this field are
memory node implementation specific.
W, 0 Reserved. Must be zero.
6 5 4 3 0
DTR RSVD
BXB-0760-93
System Registers 7-43