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3.5.4 Multiple Errors
The error registers can only hold information relative to one error. It is
the responsibility of software to read and clear all error bits and status.
Even when errors occur infrequently there is a chance that a second error
can occur before software clears all status from a previous error. The error
register descriptions specify the behavior of a node when multiple errors
occur.
Some errors are more important to software than others. For example,
should two correctable data errors occur, one during a write to memory
and the other during a read from memory, the error during the write
would be more important. The software can do no more than log the read
error as it should be corrected by hardware. But the memory location is
written with a single-bit data error. Software may rewrite that memory
location so every read of that location does not report an error in the fu-
ture.
The following priority rules apply to multiple errors:
1.
2.
3.
4.
5.
Status registers are overwritten with data only if a higher priority data er-
ror occurs. If software finds multiple data error bits set, the information in
the status registers reflects status for the highest priority error. If multi-
ple errors of the same priority occur, the information in the status regis-
ters reflects the first of the errors.
The address bus interface sets hard error bits only for the first address bus
sequence in error. Should a subsequent address bus sequence result in ad-
ditional errors, the <AE2> bit is set but other bits are unchanged. This
should help to isolate the root cause of an error from propagating errors.
The error bits that are preserved in this case are <ATCE>, <APE>, TL-
BER<BAE>, <LKTO>, <FNAE>, <NAE>, <RTCE>, <ACKTCE>, and
<MMRE>.
System fatal address bus errors are cumulative. Should a second system
fatal error condition occur, TLSB_FAULT is asserted a second time. If the
fatal error is of a different type than the first, an additional error bit sets
in the TLBER register.
<FNAE>, <APE>, <ATCE>, or <BAE> error bits in TLBER register —
highest priority
<UDE> and NAE error bits in TLBER register
<CWDE> error bit in TLBER register
<CRDE> error bit in TLBER register
Node-specific conditions — lowest priority
CPU Module 3-19
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