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5.1.1.1
Memory Bank State Machine
The CTL contains two TLSB control state machines, one for each memory
bank. The state machines receive/generate information from/to the TLSB
bus as well as other TLSB support logic and DRAM control logic. Each
state machine begins operation when a valid TLSB transaction request
destined for the particular memory bank that it supports is received. Each
state machine has two basic flows, one for memory reads and one for mem-
ory writes. The following sections list the major functions performed by the
TLSB memory bank state machine (TLSM).
5.1.1.2
CSR State Machine
The CSR TLSM is similar to the memory bank TLSM. The major differ-
ence is that the CSR TLSM shares control of the transaction with the
memory address interface (MAI) CSR sequencer rather than the DRAM
control sequencer. The CSR TLSM initiates either a CSR read or write op-
eration by starting the MAI CSR sequencer. Similar to the memory bank
TLSM, the CSR TLSM handles proper sequencing to the TLSB bus. It is-
sues TLSB_SEND_DATA and SEQ, and monitors for TLSB_HOLD
(TLSB_DIRTY is ignored for CSR read operations). It also issues the nec-
essary control to the MDI chip for proper loading and unloading of CSR
data onto the TLSB.
5.1.1.3
TLSB Input Latches
The CTL contains three sets of TLSB input latches, one for bank 0, one for
bank 1, and one for CSR operations. The input latches store the TLSB ad-
dress and command information necessary to process bus transaction re-
quests. If a particular bank is not busy and a TLSB command/address cy-
cle is determined to be destined for that bank, then the address and
command information will be held in the bank latches until the transac-
tion is processed.
5.1.1.4
TLSB Bus Monitor
The TLSB bus monitor is a simple sequencer that monitors the TLSB re-
quest lines to detect the occurrence of a command cycle. During a com-
mand cycle, the TLSB latches are opened and subsequently closed on the
following cycle. This allows the command cycle as well as the following cy-
cle to perform the necessary decode on the TLSB transaction request. If
the transaction was destined for that particular memory bank or CSR,
then the latches remain closed for the duration of the transaction.
The TLSB is in an idle state until a request is posted. The following cycle
is an arbitration cycle in which the commander nodes (CPU, I/O port) arbi-
trate for the TLSB. The command cycle follows the arbitration cycle. This
is the cycle during which the memory adapter opens the input latches of
any nonbusy bank. Note that the command cycle can also be a request cy-
cle if any requests are posted.
5.1.1.5
TLSB Command Decode
The commands received from the TLSB are decoded to determine the type
of transaction being requested. Whether the command received is a valid
5-2 Memory Interface
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