Victim Buffers; Lock Registers; State Transition Due To Tlsb Activity - DEC AlphaServer 8200 Technical Manual

4.2.7 Victim Buffers

The B-cache is a direct-mapped cache. This means that the block at a cer-
tain physical address can exist in only one location in the cache. On a read
miss, if the location is occupied by another block (with the same B-cache
index, but a different tag address) and the block is dirty (that is, the copy
in the B-cache is more up-to-date than the copy in memory), that block
must be written back to memory. The block being written back is referred
to as a "victim."
When a dirty block is evicted from the B-cache, the block is stored in a vic-
tim buffer until it can be written to memory. The victim buffer is a one-
block secondary set of the B-cache. Bus activity directed at the block
stored in the victim buffer must give the correct results. Reads hitting in
the victim buffer must be supplied with the victim data. Writes targeted
at the victim buffer must force the buffer to be invalidated.
Victims are retired from the buffer to memory at the earliest opportunity,
but always after the read miss that caused the victim. One victim buffer is
supported per CPU. If the victim buffer for the CPU is full, further reads
are not acknowledged until the buffer is free.

4.2.8 Lock Registers

To provide processor visibility of a block locked for a LDxL/STxC (load
lock/store conditional), a lock register is maintained in the CPU module.
The lock register is loaded by an explicit command from the DECchip
21164. TLSB addresses are compared against this lock register address.
One lock register is maintained for each CPU. In the event of a lock regis-
ter match on a bus write, the lock bit for that CPU is cleared and the sub-
sequent STxC from the processor fails.
If a TLSB address matches the address in the lock register, the module re-
sponds with its Shared bit set. This ensures that even if the locked block
is evicted from the cache, write traffic to the block will be forced onto the
TLSB and, in the event of a match, will cause the lock register bit to be
cleared.
4-6 Memory Subsystem

• State transition due to TLSB activity

Table 4-3 shows how the cache state can change due to bus activity.
TLSB writes always clean (make nondirty) the cache line in both the
initiating node and all nodes that choose to take the update. They also
update the appropriate location in main memory. TLSB reads do not
affect the state of the Dirty bit, because the block must still be written
to memory to ensure that memory has the correct version of the block.