Csr Write Data Ecc Check; Forcing Write Errors For Diagnostics - DEC AlphaServer 8200 Technical Manual

Figure 5-1 64-Bit ECC Coding Scheme
DATA 6666 5555
BITS 3210 9876
XOR S7 0000 0000
XOR S6 1111 1111
1111 1111
XOR S5
XOR S4 1100 0000
0011 1000
XNOR S3
1010 0110-
XNOR S2
0001 0101
XOR S1
1011 0100
XOR S0
7766 6666
HEX
50DB 8742
SYNDROME
CHECK
BITS 7654 3210
XOR S7 1000 0000
XOR S6 0100 0000
0010 0000
XOR S5
XOR S4 0001 0000
XNOR S3
0000 1000
XNOR S2 0000 0100
XOR S1
0000 0010
XOR S0
0000 0001
HEX
8421 0000
SYNDROME
0000 8421
The received write data is checked for ECC errors. Any detected error is
logged as appropriate in the TLESRn error register. No correction is made
even though a single-bit error is detected. The data is written to the
DRAMs such that each of the four bits stored in each DRAM is protected
by a different set of ECC bits. Thus, when a whole chip DRAM failure oc-
curs, the failure results in single-bit errors in four different quadwords
rather than one or more uncorrectable error(s).
5.2.2.3

CSR Write Data ECC Check

CSR data transfers are protected by the same ECC code as memory data
transfers. However, single-bit errors detected on CSR writes are not cor-
rected by the memory. The detection of any data error on CSR writes to
memory causes the write to be aborted and the error to be logged in the
MDI TLESR as an uncorrectable ECC error.
5.2.2.4

Forcing Write Errors for Diagnostics

The write data path includes the means of inverting any one of the re-
ceived data bits and/or any one of the received check bits. The inversion
takes place between the time the data is received from the TLSB and its
being written to memory. Thus, good data can be received from the TLSB
and written to memory with a single- or double-bit error forced. This cor-
ruption of write data occurs only when the TLSB write address matches
the address in the CTL MDRB register. It is controlled by the MDI DDR
register.
5-10 Memory Interface
5555 5544 4444 4444 3333
5432 1098 7654 3210 9786
1111 1111 1111 1111 0000
0000 0000 0000 0000 1111
0000 0000 1111 1111
0000
1111 1100 1100 0000 1111
1110 0011 0011 1000 1110
1001 1001 1010 0110 1001
0101 0111 0001 0101 0101
1101 0001 1011 0100 1101
9999 9988 BBAA AAAA 5555
DB87 42AF 50DB 8742 DB87
3322 2222 2222
3333 1111
5432 1098 7654 3210 9876
1111 1111 0000
0000 0000
1111 1111 1111 0000 0000
1111 1111 0000
1111 0000
1100 0000 1111
1100 1100
0011 0011 1000 1110
0011
1010 0110 1001
1001 1001
0001 0101 0101
0111 0111
0001 0100 1011 0010 1110
FFEE EEEE 1111
5544 1100
42AF 41CA 9653 CA96 53BE
1111 11
5432
1098 7654 3210
0000 0000 1111 1111
0000 0000 1111
1111
1111 1111 0000 0000
1100 0000 1111 1100
0011 1000 1110 0011
1010 0110 1001 1001
0001 0101 0101 0111
0100 1011
0010 1110
3322 2222 DDDD DDCC
41CA 9653 CA98 53BE
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