Write Data Out Selection; Read Data Output Logic; Read Data Buffers; Read Data Path Ecc Algorithm - DEC AlphaServer 8200 Technical Manual

5.2.2.5

Write Data Out Selection

A 2:1 multipexer and a tristate enable capability are provided for interfac-
ing the write data buffers to the DRAM array bus. The multiplexer allows
the selection of data from either the bank 0 or the bank 1 buffers. The tri-
state enable capability allows the write data output to the DRAM array
bus to be disabled so that it may be used for receiving read data.

5.2.3 Read Data Output Logic

The read data output logic receives data from the DRAM array or the
CSRs and transmits it onto the TLSB at the appropriate time. Temporary
storage is provided for the DRAM read data, so that the DRAM cycle may
complete even though the TLSB is not yet ready to receive the read data.
5.2.3.1

Read Data Buffers

The read data buffer in each MDI consists of four 72-bit data storage ele-
ments, two dedicated to each bank. Each of these quadword data buffers
consists of 8 bytes of data and the 8 ECC bits associated with them. Each
MDI receives 144 bits of read data from the DRAM array each time a bank
is read. The lower half of these is loaded into that bank's quadword 0
buffer while the upper half is loaded into the quadword 1 buffer. Each
buffer temporarily stores the data read until the TLSB is ready to return it
to the requesting node.
5.2.3.2

Read Data Path ECC Algorithm

The read data and ECC bits are read from the DRAMs in the format to be
transmitted onto the TLSB except for the inclusion of address parity in the
stored ECC bits. The effects of address parity are removed from the ECC
bits before the transmission of data onto the TLSB. The integrity of the
data is also checked by verification of the ECC bits to aid in error isolation,
even though no corrective action is taken when an error is detected. This
ECC check on read data is implemented after the data has been driven
onto the TLSB, so that the same ECC logic can be used that is used to
check for write ECC errors. The implication of this implementation is that
there must be no transmit check error (TCE) for the logged correctable or
uncorrectable read ECC error to be attributed to the memory. If a TCE is
logged by the memory along with a read ECC error, then the ECC error
must be assumed to be due to corruption of the data on the TLSB. Syn-
dromes and error indicators are logged in their TLESRn register.
Since address parity was encoded in the ECC bits prior to their storage in
the DRAMs, it must be removed before the ECC bits can be transmitted
onto the TLSB. To facilitate the removal of address parity, row and col-
umn parity bits must be generated by the CTL for each received read com-
mand and transmitted to MDI. MDI latches both row and column parity
bits for each bank as they are received with the assertion of
DSM_LD_DRAM_DATA.
5.2.3.3

CSR Read Data ECC

CSR data is transmitted onto the TLSB protected by the same ECC code as
that for memory data transfers. Zeros are transmitted on TLSB_D<63:32>
Memory Interface 5-11